Digital VCO Phase Control for Low-Jitter PLL Clocks
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Solution Overview
Problem
Conventional digital VCO circuits in data recording apparatuses face challenges in controlling the output timing of clock signals finer than the period of a reference clock signal, leading to phase errors and spurious bands that result in jitter, which hinders high-quality data recording and reproduction.
Innovation Solution
A PLL circuit with a phase comparing section, low pass filter, and digital VCO circuit that operates in synchronism with a reference clock signal, using frequency division and phase modulation to generate a sync clock signal with improved phase resolution, allowing for finer control of clock signal timing through a delay line or multi-phase signal generation and averaging processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the frequency of the reference clock signal is increased to improve output frequency resolution of the digital VCO, then the frequency resolution improves, but the reference clock signal becomes susceptible to noise and waveform distortion, causing logic circuit operation instability
Solution Approach 1:
The patent segments the phase control function into two independent parts: (1) frequency control through the digital VCO operating at normal reference clock frequency, and (2) fine phase adjustment through a separate delay line controlled by phase difference data. This segmentation allows the reference clock frequency to remain low and stable while achieving high phase resolution through the delay line's time-delay capability.
Solution Approach 2:
The patent introduces a delay line as an intermediary component between the digital VCO and the output. The delay line converts phase difference data into actual time delays, acting as a mediator that translates digital control signals into precise timing adjustments without requiring high reference clock frequencies.
2Device complexity
If conventional digital VCO output timing control is used, then the circuit complexity remains low, but phase errors and spurious bands occur, resulting in jitter that degrades data recording quality
Solution Approach 1:
The patent divides the clock signal generation and control functions into distinct modules: a digital VCO for frequency control, a phase comparing section for detecting phase differences, and a delay line for precise timing adjustment. This modular segmentation achieves high timing precision while keeping each module relatively simple and manageable.
Solution Approach 2:
The patent replaces direct high-frequency timing control (which would require complex high-speed logic circuits) with a delay-based approach using a delay line. This substitution uses controlled time delays instead of relying on high-frequency signal edges, simplifying the overall circuit while improving timing precision.
3Measurement precision
If the digital VCO operates at high reference clock frequency to achieve fine phase control, then phase precision improves, but the adder operation frequency limit is exceeded and noise susceptibility increases
Solution Approach 1:
The patent separates phase precision control from reference clock frequency by introducing a delay line that operates independently of the reference clock speed. The digital VCO operates at a moderate frequency suitable for adder operations, while the delay line provides fine phase adjustment without being constrained by high-frequency operation limits.
Solution Approach 2:
The delay line serves as an intermediary that decouples the relationship between reference clock frequency and phase precision. It translates phase difference data into precise time delays without requiring the reference clock to operate at high frequencies, thus avoiding the limitations of adder operation speed and noise susceptibility.
Data Source
AI summary
A PLL circuit includes a phase comparing section, a low pass filter, a digital VCO circuit, and a frequency divider. The phase comparing section compares an inputted clock signal and a frequency-divided clock signal in phase to detect a phase difference. The low pass filter averages the phase difference outputted from the phase comparing section to output the averaged result as a frequency control input. The digital VCO circuit operates in synchronism with a reference clock signal, and generates a sync clock signal based on the frequency control input while a phase of the sync clock signal is controlled in units of predetermined resolution values. The predetermined resolution value is a 1/K (K is a natural number more than 1) of a period of the reference clock signal. The frequency divider frequency-divides the synch clock signal to generate the frequency-divided clock signal.