Digital VFC Circuit for Accurate Failbit Counting
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Solution Overview
Problem
Existing VFC circuits in memory devices occupy space and increase power consumption, and their accuracy is affected by factors like power drop, transistor mismatch, and signal routing, leading to undercounting and yield loss.
Innovation Solution
A digital VFC circuit incorporating a counter circuit to count fail bits in unary format and a transcoder to transcode the result to binary format, eliminating reliance on current sensing and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If analog method is used to sense failbit numbers, then the VFC circuit can be implemented with simpler structure, but current consumption increases and measurement precision deteriorates due to power drop, transistor mismatch, and signal routing issues
Solution Approach 1:
The patent replaces the analog current-based sensing system with a digital voltage-based counting system. Instead of using analog current sensing that is susceptible to power drop and transistor mismatch, the invention uses digital logic circuits (AND gates, OR gates, D flip-flops) to count failbits through voltage level detection, thereby eliminating the measurement precision issues while maintaining implementation simplicity
Solution Approach 2:
The patent changes the sensing parameter from current (analog) to voltage (digital). By detecting voltage levels rather than measuring current magnitudes, the system avoids the problems of power drop and transistor mismatch that affect current-based analog sensing, thus improving measurement precision without significantly increasing circuit complexity
2Device complexity
If analog current sensing is used in VFC circuit, then the circuit implementation is straightforward, but power consumption increases due to continuous current flow requirements
Solution Approach 1:
The patent implements periodic action by using clocked D flip-flops that update their state only at specific clock edges. The digital counting circuit operates in discrete time steps rather than continuously, allowing the circuit to consume power only during state transitions rather than maintaining continuous current flow, thus reducing overall power consumption while keeping implementation straightforward
3Measurement precision
If digital counter circuit is used to count failbits, then measurement precision improves, but device complexity increases due to additional logic gates and transcoders
Solution Approach 1:
The patent segments the digital counting function into modular components: individual AND gates for each memory string, OR gates for combining results, and D flip-flops for state storage. This segmentation allows each component to perform a simple, well-defined function, making the overall circuit easier to design and verify while achieving high measurement precision through the coordinated operation of these simple modules
Data Source
AI summary
A verify fail bit count (VFC) circuit includes a power-supply transistor, a sense stage coupled to the power-supply transistor and configured to, in response to a verification operation, sense each of a plurality of verification bits being a fail bit or a pass bit, a plurality of storage stages coupled to the sense stage in parallel and each configured to store one fail bit sensed by the sense stage based on a sequence from near to far from the sense stage, and a common ground transistor coupled to the sense stage and the plurality of storage stages.