Digital Verify Failbit Count Circuit for Memory Yield
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Solution Overview
Problem
Existing Verify Fail bit Count (VFC) circuits in memory devices are space-consuming, increase power consumption, and are prone to undercounting due to factors like power drop, transistor mismatch, and signal routing issues when using analog methods.
Innovation Solution
A digital VFC circuit that sequentially receives bit groups containing verification bits, using a counter with multiple stages to count fail bits accurately, and performs a determination process based on the position of each verification bit to select the appropriate counter stage for writing fail bits or discarding them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog method is used to sense failbit numbers, then the VFC circuit can be implemented, but current consumption increases and measurement precision deteriorates due to power drop, transistor mismatch, and signal routing issues
Solution Approach 1:
The patent replaces the analog sensing method with a digital counting method. Instead of using analog current sensing that is susceptible to power drop and transistor mismatch, the invention uses digital logic circuits (AND gates, OR gates, D-flip flops) to count fail bits. This substitution of analog mechanical sensing with digital logic eliminates the harmful effects of analog signal degradation while maintaining the VFC function, thereby improving measurement precision without excessive power consumption.
Solution Approach 2:
The patent changes the operating parameters from analog current levels to digital logic levels. By transitioning from continuous analog signals to discrete digital states (0 and 1), the system avoids the accumulation of analog errors due to power drop and transistor mismatch. The digital parameters are more robust against variations and provide accurate counting of fail bits.
2Manufacturing precision
If analog method is used to sense failbit numbers, then the VFC circuit can be implemented, but manufacturing precision deteriorates due to transistor mismatch and signal routing issues
Solution Approach 1:
The patent replaces the analog sensing circuit with a digital logic circuit. The digital implementation using logic gates and flip-flops is less sensitive to manufacturing variations and transistor mismatch compared to analog circuits. Digital logic has well-defined switching thresholds that are more tolerant of process variations, thereby improving counting accuracy despite the increased gate count.
Solution Approach 2:
The patent segments the fail bit counting process into multiple stages using separate logic units. Each stage handles specific bit positions or groups of bits, allowing the complex counting function to be divided into manageable digital logic blocks. This segmentation reduces the complexity of any single analog sensing path and improves overall manufacturing precision.
3Productivity
If VFC circuit is added to memory device, then failbit counting function is provided, but space requirements increase
Solution Approach 1:
The patent implements a VFC circuit that can be integrated with existing memory device structures to perform fail bit counting. The digital logic components (AND gates, OR gates, D-flip flops) are designed to be compact and can share resources with other memory device functions, reducing the overall area impact while providing the necessary yield improvement through accurate fail bit counting.
Data Source
AI summary
A failbit counting method includes sequentially receiving, at an input of a counter, a bit group including one or more verification bits. Each of the one or more verification bits is a fail bit or a pass bit. The counter includes one or more counter stages coupled in series from the input. The method further includes, for one verification bit of the one or more verification bits, performing a determination process according to a position of the one verification bit in the group to select one of the one or more counter stages for writing a fail bit or to decide to discard the one verification bit.