Digitally Controlled Oscillator With Linear Frequency Tuning
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Solution Overview
Problem
Digital PLL circuits require a wide operating range and efficient frequency tuning, but existing digitally controlled oscillators (DCOs) face challenges in linearizing the output clock signal, particularly at lower supply voltages, due to non-linear variations in resistance values affecting frequency and phase noise performance.
Innovation Solution
A digitally controlled oscillator with a ring oscillator and variable resistance banks composed of transistors, where the resistance values are controlled by a digital code, allowing for linear frequency adjustments by varying the number of active bits, ensuring the frequency of the output clock signal changes linearly with the resistance value, and using different ON-resistance transistors to achieve non-linear reciprocal relationships for precise frequency control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a digitally controlled oscillator uses a delay line with series-connected inverters to generate oscillation signals, then the frequency tuning range can be adjusted by controlling delay time, but the output clock signal frequency varies non-linearly with control code due to resistance value variations
Solution Approach 1:
The patent applies parameter changes by modifying the resistance values of transistors in the delay line based on control code. Specifically, the resistance value of each transistor is adjusted according to its control bit state, allowing the delay time to be controlled in a manner that produces linear frequency output. This transforms the non-linear resistance-frequency relationship into a linear control mechanism.
2Productivity
If the resistance value of transistors in the delay line is varied to adjust frequency, then frequency control is achieved, but phase noise performance deteriorates due to non-linear resistance variations
Solution Approach 1:
The patent applies local quality by assigning different resistance values to different transistors based on their position in the delay line and their control bit significance. Each transistor contributes differently to the total delay time, with transistors controlled by less significant bits having larger resistance values. This localized differentiation ensures that each control bit contributes linearly to the frequency adjustment while maintaining stable phase noise characteristics.
3Adaptability or versatility
If a wide operating range is required for digital PLL circuits, then frequency tuning range must be expanded, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The patent applies segmentation by dividing the frequency control into multiple independent control bits, each controlling a specific transistor in the delay line. This segmentation allows the wide operating range to be achieved through combinations of discrete control steps rather than requiring a single complex continuous control mechanism. Each control bit independently adjusts the delay time contributed by its associated transistor, simplifying the overall control architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a digitally controlled oscillator with a wide operating range and linear frequency adjustments, enhancing the frequency tuning range and phase noise performance, while maintaining low power consumption by controlling the total resistance value without independently adjusting delay cells.
Implementation Method 1
a first variable resistance bank connected with one power node of the ring oscillator and having its resistance value varied according to the number of active bits of a control code
Implementation Method 2
The DCO generates an oscillation signal by feeding back a delayed signal output from the delay line to an input terminal of the delay line
Data Source
AI summary
Disclosed is a digitally controlled oscillator which includes a ring oscillator; and a variable resistance bank connected between one power node of the ring oscillator and a power supply terminal and having the resistance value varied according to the number of active bits of a control code. The frequency of an clock signal output by the ring oscillator is changed non-linearly according to the resistance value of the variable resistance bank. The frequency of the output clock signal is changed stepwise linearly according to the number of active bits of the control code.