Digitally Controlled Varactor for High Resolution DCO
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Solution Overview
Problem
Conventional MOS varactors face limitations in fine frequency tuning resolution and are plagued by parasitic diode leakage and narrow tuning ranges, particularly in n-MOS accumulation-type and inversion MOS varactors, which affect their performance in modern communication systems.
Innovation Solution
A digitally controlled varactor device utilizing a set of bulk nMOS or FDSOI nMOS field effect transistors, configured with specific transistor connections and backgate voltage control, eliminates parasitic diode current leakage and enhances capacitance tuning resolution, allowing for a wider tuning range without AC coupling capacitors or DC bias resistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If n-MOS accumulation-type varactor is used, then implementation is simple, but parasitic diode leakage occurs when Vcontrol exceeds threshold voltage
Solution Approach 1:
The varactor is divided into multiple fingers (e.g., three fingers) with separate gates and channels. This segmentation allows independent control of each finger's capacitance contribution, enabling the total capacitance to be adjusted in fine increments while maintaining low leakage through proper biasing of individual fingers.
Solution Approach 2:
The invention dynamically adjusts the control voltage applied to each finger's gate to optimize performance. By varying the control voltage, the varactor can operate in different regions (accumulation, depletion, inversion) to minimize parasitic leakage while maintaining the desired capacitance value, thus dynamically adapting to different operating conditions.
2Adaptability or versatility
If conventional MOS varactor is used, then voltage controlled capacitance is achieved, but tuning range is narrow and frequency resolution is limited
Solution Approach 1:
The multi-finger structure with independently controllable gates enables fine-grained adjustment of total capacitance. Each finger contributes a discrete capacitance value, and by selectively activating or adjusting individual fingers, the total capacitance can be tuned with high resolution across a wide range, thereby achieving both wide tuning range and high frequency resolution.
Solution Approach 2:
The invention changes the capacitance parameter by adjusting the control voltage applied to the gates of the MOS transistors. By varying the gate voltage, the capacitance of each finger is continuously adjustable, enabling wide tuning range. The discrete nature of the finger structure provides inherent quantization that achieves high frequency resolution without requiring excessive voltage precision.
3Adaptability or versatility
If control voltage is increased to expand tuning range, then capacitance range increases, but parasitic diode turns on and causes current flow
Solution Approach 1:
The control voltage is dynamically optimized for each finger to achieve the desired capacitance while keeping the parasitic diodes reverse-biased or at least not strongly forward-biased. By carefully managing the control voltage levels and the segmentation of capacitance across multiple fingers, the system expands the usable tuning range without activating parasitic current paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a fine frequency tuning resolution of approximately 22 aF capacitance change per step and a 23 fF tuning range, reducing phase noise and parasitic capacitance, while maintaining a high Q factor across the tuning range.
Implementation Method 1
Metal oxide semiconductor (MOS) varactors may have a control voltage applied to a gate terminal that provides a control on the capacitance obtained for a particular voltage applied on the remaining terminals of the device
Implementation Method 2
Because a varactor is based on a reverse biased P-N junction, the terminals are typically biased such that no current flows across the P-N junction, thereby forming a capacitor
Implementation Method 3
Varying the bias on the gate of a MOS varactor causes the formation of a depletion or an accumulation region under the gate, changing the current flow through the varactor
Data Source
AI summary
A digitally controlled varactor device comprising: a set of bulk nMOS field effect transistors bulk tied to a ground, the set bulk nMOS field effect transistors having: a first transistor including: a source coupled to a DC voltage source; and a gate coupled to a digitally controlled oscillator; a second transistor including: a source coupled to the DC voltage source; and a gate coupled to the digitally controlled oscillator; and a third transistor including: a source coupled to a drain of the first transistor; and a drain coupled to a drain of the second transistor. The transistors in the digitally controlled varactor may be FDSOI nMOS devices with backgate coupled to a DC voltage source.