Digitally Tuned Capacitor Cell Layout for High-Power RF Matching
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Solution Overview
Problem
Integrated circuit devices face challenges with poor tolerance values in passive electrical components, leading to performance degradation under varying operating conditions, especially at high frequencies, and existing tunable matching networks fail to meet power handling and linearity requirements for mobile handsets.
Innovation Solution
A digitally tuned capacitor (DTC) is implemented using a stack of FETs and MIM capacitors, with a unit cell design technique that allows for binary weighting and thermometer coding, enabling precise capacitance control and improved power handling, linearity, and reduced die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a bank of switches is used to selectively couple capacitors in a prior art approach, then capacitance can be adjusted to desired values, but significant loss is introduced into the tuned circuit at high frequencies degrading performance
Solution Approach 1:
The patent extracts the switching function from separate discrete switches and integrates it directly into the capacitor structure by forming capacitive elements within the semiconductor substrate. This integration eliminates the need for separate switch components that introduce loss, while maintaining the ability to selectively couple capacitors through integrated control mechanisms.
Solution Approach 2:
The patent merges the capacitor and switch functions into a single integrated structure where capacitive elements are formed directly in the semiconductor substrate. This combining of functions reduces the number of discrete components and their associated losses, particularly at high frequencies, while preserving adaptability through integrated control.
2Manufacturing precision
If post-fabrication trimming techniques are used to physically alter the circuit, then tolerance values can be improved, but only static solutions are produced that may not perform adequately under all operating conditions
Solution Approach 1:
The patent implements dynamic tuning capability by providing control mechanisms that allow the capacitive elements to be adjusted during operation. The integrated circuit includes control logic that can modify the effective capacitance values based on operating conditions, enabling the circuit to adapt and maintain optimal performance across varying environments rather than being fixed to nominal conditions.
Solution Approach 2:
The patent enables continuous parameter adjustment of capacitance values through integrated control mechanisms. By changing the effective capacitance parameters dynamically based on operating conditions, the circuit maintains optimal performance across different frequencies, temperatures, and load conditions, overcoming the static nature of post-fabrication trimming.
3Manufacturing precision
If discrete external passive electrical components are used, then tolerance values are acceptable, but integration with on-chip components is difficult and costly
Solution Approach 1:
The patent replaces discrete external passive components with capacitive elements formed directly within the semiconductor substrate using standard integrated circuit fabrication processes. This substitution eliminates the need for separate discrete components and their associated mounting, wiring, and alignment operations, significantly reducing manufacturing complexity and cost while achieving comparable or superior tolerance values through integrated process control.
Solution Approach 2:
The patent creates a multi-functional integrated structure that combines capacitor formation with the existing semiconductor manufacturing process. The same fabrication processes used for transistors and interconnects are also used to form the capacitive elements, allowing passive components to be manufactured alongside active components in a unified process, thereby reducing overall manufacturing difficulty and cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The DTC achieves efficient capacitance tuning across a wide range, meeting stringent power handling and linearity requirements, while minimizing die area and maintaining constant Q-factor values, thus addressing the limitations of prior art solutions.
Implementation Method 1
A digitally tuned capacitor (DTC) is implemented using a stack of FETs and MIM capacitors
Data Source
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AI summary
A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF- terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB. Each significant bit of the digital control word is coupled to corresponding and associated significant bit sub-circuits of the DTC, and thereby controls switching operation of the associated sub-circuit. DTCs are implemented using unit cells, wherein the LSB sub-circuit comprises a single unit cell. Next significant bit sub-circuits comprise x instantiations of the number of unit cells used to implement its associated and corresponding previous significant bit sub-circuit, wherein the value x is dependent upon a weighting coding used to weight the significant bit sub-circuits of the DTC. DTCs may be weighted in accordance with a binary code, thermometer code, a combination of the two, or any other convenient and useful code. In many embodiments, the unit cell comprises a plurality of stacked FETs in series with a capacitor. The unit cell may also include a plurality of gate resistors RG coupled to the gates of the stacked FETs, and a plurality of RDS resistors coupled across the drain and source of the stacked FETs. The stacked FETs improve the power handling capabilities of the DTC, allowing it meet or exceed high power handling requirements imposed by current and future communication standards.