Digitally Tuned Capacitor Circuit for RF Power Handling

The patent applies preliminary action by incorporating trimming structures (fuses, Zener diodes, laser trim regions) directly into the fabrication process rather than requiring separate post-fabrication steps. The trim structures are formed during standard CMOS fabrication, allowing tolerance adjustment to be performed automatically during manufacturing without additional complex processing steps.

The patent replaces mechanical/post-fabrication trimming methods with electrical/photonic structures that can be formed using standard semiconductor fabrication techniques. Instead of mechanical laser trimming or electrical Zener-zapping after fabrication, the invention uses photolithographically defined trim regions and fuses that are created during the fabrication process itself, substituting complex post-fabrication operations with integrated fabrication-step solutions.

The patent merges the capacitor structure with the matching network circuitry by integrating the capacitor directly into the CMOS process flow alongside the matching network components. This consolidation allows shared fabrication infrastructure and reduces overall device area compared to using separate discrete capacitors or conventional large-area capacitor implementations.

The patent changes the physical and electrical parameters of the capacitor by using stacked FETs in series to achieve high voltage tolerance (±2.5V or higher) without requiring large physical area. The series connection of FETs divides the voltage stress across multiple devices, allowing the use of smaller, more area-efficient capacitor structures that can handle high power while maintaining compact dimensions suitable for integrated circuits.

The patent segments the capacitor into multiple discrete units (stacked FETs with associated capacitors) that can be independently controlled through digital selection. Each FET-capacitor pair represents a discrete tuning step, allowing the overall capacitance to be adjusted in controlled increments. This segmentation enables digital control while keeping each individual unit simple and fabrication-friendly.

The patent creates a universal building block (FET stacked in series with capacitor) that serves multiple functions: it provides capacitance tuning, voltage tolerance handling, and digital controllability all in one structure. This multi-functional unit can be replicated and combined to achieve different capacitance values and tuning ranges, reducing overall device complexity compared to implementing separate circuits for each function.

The patent uses FETs that are fabricated using the same CMOS process steps and are located in close proximity to each other, ensuring they have matched electrical characteristics. The series stacking of these homogeneous FETs provides predictable voltage division and tolerance accumulation, reducing the impact of parameter variations. The matched FETs are designed to have similar threshold voltages and transconductance characteristics, which simplifies the overall circuit behavior.

The patent incorporates feedback mechanisms where the digital control system monitors and adjusts the capacitance values to compensate for manufacturing variations in the stacked FETs. By using digital control words to select and combine different FET-capacitor units, the system can dynamically compensate for parameter mismatches, ensuring consistent performance despite variations in individual FET characteristics.