Digitally Tuned RF Capacitor Array for Passive Tolerance Correction
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Solution Overview
Problem
Existing integrated circuit devices face challenges with poor tolerance values of passive electrical components, leading to difficulties in implementing tuned networks without post-fabrication trimming techniques, and requiring solutions that can dynamically monitor and correct performance characteristics under varying operating conditions.
Innovation Solution
A method and apparatus for digitally tuning a capacitor in an integrated circuit device, utilizing a Digitally Tuned Capacitor (DTC) with a plurality of sub-circuits ordered from least significant bit to most significant bit, coupled in parallel, and controlled by a digital control word to adjust capacitance between RF terminals, implemented using unit cells with stacked FETs and MIM capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If post-fabrication trimming techniques are used to improve tolerance values of passive components, then manufacturing precision is improved, but device complexity and ease of manufacture deteriorate due to additional processing steps
Solution Approach 1:
The patent applies preliminary action by pre-configuring binary-weighted capacitor arrays and switch networks during standard CMOS fabrication, eliminating the need for post-fabrication trimming. The capacitor banks are designed with predetermined values (C, 2C, 4C, 8C) that enable digital tuning without additional processing steps, thereby maintaining manufacturing simplicity while achieving high precision.
Solution Approach 2:
The patent replaces mechanical post-fabrication trimming methods (such as laser trimming or fuse cutting) with an electronic digital control system. The mechanical alteration of component values is substituted by electronic switching of pre-fabricated capacitor arrays controlled by digital signals, eliminating complex mechanical processing while achieving precise component tuning.
2Manufacturing precision
If digitally tuned capacitor arrays are used to improve tolerance values, then manufacturing precision is improved, but device complexity increases due to additional circuit components
Solution Approach 1:
The patent applies segmentation by dividing the total capacitance requirement into multiple binary-weighted segments (capacitor banks with values C, 2C, 4C, 8C). Each segment can be independently switched via dedicated control signals, allowing precise adjustment of total capacitance. This segmentation enables high precision tuning while using standard CMOS fabrication techniques, balancing precision requirements with manufacturing simplicity.
Solution Approach 2:
The digitally tuned capacitor array serves multiple functions: it provides precise capacitance tuning for frequency compensation, enables adaptive impedance matching, and supports dynamic range adjustment. The same binary-weighted capacitor structure is used across different circuit applications (operational amplifiers, voltage-controlled oscillators), reducing overall device complexity through a universal tuning mechanism.
3Ease of manufacture
If standard CMOS fabrication is used to maintain ease of manufacture, then ease of manufacture is maintained, but manufacturing precision deteriorates due to poor tolerance values of passive components
Solution Approach 1:
The patent uses copying by replicating the same unit capacitor structure multiple times with binary weighting (1x, 2x, 4x, 8x copies). Instead of relying on precise fabrication of single large-capitance components with poor tolerances, the design copies small, well-matched unit capacitors in parallel combinations. This copying approach achieves high precision capacitance values using standard CMOS processes, as the unit capacitors can be tightly matched during fabrication.
Solution Approach 2:
The patent applies parameter changes by transforming the capacitance control from a continuous analog parameter to a discrete digital parameter. Instead of adjusting a single capacitor value continuously (which is sensitive to fabrication variations), the design changes the effective capacitance by switching discrete binary-weighted capacitor banks. This parameter transformation enables precise capacitance control despite variations in individual component values during CMOS fabrication.
Data Source
AI summary
A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.