Digitizer Error Recovery via FPGA Link Reset Without Power Cycling
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Solution Overview
Problem
Existing digitizers, such as the M5200A PXIe Digitizer, require power cycling to recover from erroneous data samples caused by input signals outside the permissible voltage range, which is inconvenient and disruptive.
Innovation Solution
An in-built error detection and recovery mechanism in the digitizer, utilizing a JESD IP controller, displays error messages and adjusts the input signal voltage within a permissible range, allowing the data link to be reset without power cycling, ensuring transparent self-recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power cycling is performed to recover from erroneous data samples, then the digitizer can restore correct data capture, but the operation is inconvenient and disruptive
Solution Approach 1:
The digitizer system performs self-diagnosis and self-recovery through the IP controller detecting link errors and automatically resetting the data link without requiring user intervention for power cycling. The system serves itself by monitoring its own operational state and initiating recovery procedures autonomously.
Solution Approach 2:
The error detection mechanism continuously monitors data samples for errors before they propagate through the system. When errors are detected, the IP controller initiates link reset procedures in advance, preventing the need for disruptive power cycling operations later.
2Ease of operation
If the data link is reset without power cycling, then operational convenience is improved, but the complexity of the recovery mechanism increases
Solution Approach 1:
The IP controller serves as an intermediary component between the ADC and FPGA, handling error detection and link reset operations. This mediator absorbs the complexity of error recovery mechanisms, allowing the rest of the system to remain simple while providing sophisticated error handling capabilities.
Solution Approach 2:
The patent replaces the mechanical/power-based recovery method (power cycling) with an electronic/software-based approach. The IP controller uses digital signal processing and control logic to detect and recover from errors, substituting physical power cycle operations with electronic link reset sequences.
3Measurement precision
If error detection is continuously performed, then data accuracy is improved, but the processing overhead increases
Solution Approach 1:
The IP controller performs error detection on critical portions of the data stream (data samples from ADC) rather than exhaustive checking of all data. This partial action approach maintains high sampling throughput while providing sufficient error detection capability to ensure data accuracy where it matters most.
Data Source
AI summary
A digitizer includes an analog-to-digital converter (ADC), a field programmable gate array (FPGA), a data link of a given interface standard between the ADC and the FPGA, and a display device operatively connected to the FPGA. The FPGA includes an IP controller configured according to the interface standard of the data link. An error detection and recovery method for the digitizer includes applying an analog input source signal to the ADC, acquiring data samples on the data link from the ADC to the FPGA, and the IP controller checking the data samples for errors. When the data samples include errors, the method further includes (a) the IP controller displaying on the display device a waveform of the captured data samples and an error message, (b) a user adjusting a voltage of the input signal source to within a given peak-to-peak voltage range, and (c) the IP controller resetting the data link without power cycling of the digitizer. When the data sample does not include errors, the method includes displaying on the display device a waveform of the captured data samples.