Dilithium Modular Reduction Circuit With Single-Multiplier Architecture
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Solution Overview
Problem
The advent of quantum computers poses a significant threat to the security of existing public-key cryptosystems, such as RSA and ECC, as they can be potentially broken by Shor's algorithm, necessitating a transition to post-quantum cryptosystems to ensure long-term security in cloud computing.
Innovation Solution
Implementing a hardware-friendly modular reduction architecture for lattice-based cryptosystems using Number Theoretic Transform (NTT) and Inverse Number Theoretic Transform (INTT) operations, which reduce computational complexity by leveraging the prime value of q=8,380,417, and utilizing a single multiplier with customized adders and subtractors to perform modular multiplication efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional modular multiplication architecture is used, then computational correctness is ensured, but hardware complexity and resource usage increase
Solution Approach 1:
The patent segments the modular multiplication operation into distinct functional blocks: a non-modular multiplier, multiple non-modular adders, a modular adder, and a modular subtractor. This segmentation allows each component to perform a specific function independently, simplifying the overall hardware design while maintaining computational correctness through the modular reduction process.
Solution Approach 2:
The patent introduces intermediate results as a mediator mechanism. The multiplier first produces an intermediate product, which is then processed through a sequence of adders and subtractors to produce the final modular result. This intermediate representation allows the system to break down the complex modular multiplication into simpler operations, reducing hardware complexity while ensuring correctness.
2Productivity
If multiple multipliers are used for modular multiplication, then computational speed is improved, but hardware resource usage increases
Solution Approach 1:
The patent merges multiple functional operations into a single non-modular multiplier. Instead of using separate multipliers for different operations, the design combines the multiplication and subsequent addition/subtraction operations into a unified architecture that uses one multiplier followed by a sequence of adders and subtractors, thereby reducing hardware resource usage while maintaining computational efficiency.
Solution Approach 2:
The patent implements continuous processing where the output of one operation feeds directly into the next operation without interruption. The multiplier produces an intermediate result that immediately becomes input for the adders, which then feed into the modular adder and subtractor. This continuous pipeline approach eliminates idle cycles and optimizes computational speed while using fewer hardware resources.
3Reliability
If standard modular reduction algorithm is used, then computational correctness is ensured, but time complexity increases
Solution Approach 1:
The patent performs preliminary actions by pre-computing and storing the modulus value (q = 8,380,417) and its bit representation in the hardware architecture. This preliminary preparation allows the modular reduction to be performed more efficiently during actual computation, as the system can directly use the pre-stored modulus values without requiring complex runtime calculations, thereby reducing time complexity while maintaining correctness.
Data Source
AI summary
Devices, systems, and methods for modular multiplication are provided. A circuit for modular multiplication can include a single multiplier configured to receive two variables and produce a product of the two variables, first adders configured to receive one or more subsets of contiguous bits of the product and generate sums based on received subsets of contiguous bits, second adders configured to receive at least a portion of the sums from the first adders and generate intermediate sums, a customized adder configured to receive another, different subset of contiguous bits of the product and an intermediate sum of the intermediate sums and generate a sum based on the received subset of contiguous bits and the intermediate sum, and a subtractor configured to receive the sum from the customized adder and another intermediate result of the intermediate results and generate a result that is the product modulo a prime number, q=8,380,417.