DIMM Clock Driver Protocol Detection for Jitter-Stable Compatibility
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Solution Overview
Problem
Dual in-line memory modules (DIMMs) without on-board clock drivers face compatibility issues with both conventional and new host controllers due to increased clock signal frequency, leading to severe jittering problems.
Innovation Solution
A clock driver with a clock detector, phase locking loop (PLL) module, and multiplexers that receive input clock signals, generate protocol identifiers, and selectively output either the input or reference clock signals to ensure compatibility and mitigate jittering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock signal frequency is increased to improve data transmission speed, then productivity is improved, but clock signal jittering becomes more severe
Solution Approach 1:
A clock driver is introduced as an intermediary component between the host controller and memory chips. The clock driver receives clock signals from the host controller and generates buffered clock signals to drive the memory chips, isolating the memory chips from direct exposure to high-frequency jittering signals while enabling high-speed data transmission
2Reliability
If a clock driver is added to mitigate jittering, then clock signal stability is improved, but device complexity increases
Solution Approach 1:
The clock driver integrates multiple functions including clock signal reception, protocol detection, signal buffering, and clock generation into a single component. This merging of functions reduces the overall system complexity compared to having separate components for each function while still providing jitter mitigation
3Reliability
If DIMMs are designed to work with new host controllers providing clock signals via clock driver, then clock signal stability is improved, but adaptability to both new and conventional host controllers becomes challenging
Solution Approach 1:
The clock driver is designed with universal functionality to detect different clocking protocols and adapt its operation accordingly. It can operate in different modes: passing through clock signals directly when receiving from conventional host controllers, or generating buffered clock signals when receiving from new host controllers, thereby maintaining compatibility with both types while providing jitter mitigation when needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The clock driver enables DIMMs to work seamlessly with both conventional and new host controllers, effectively addressing backward compatibility and reducing clock signal jittering, especially in high-frequency environments.
Implementation Method 1
a phase locking loop (PLL) module coupled to receive at least one pair of the plurality pairs of input clock signals, and for generating at least one pair of reference clock signals according to the received at least one pair of input clock signal
Data Source
AI summary
A clock driver comprises: a clock detector for receiving a plurality pairs of input clock signals of a predetermined clocking protocol, and for generating a protocol identifier indicative of the predetermined clocking protocol; a phase locking loop (PLL) module coupled to receive at least one pair of the plurality pairs of input clock signals, and for generating at least one pair of reference clock signals according to the received at least one pair of input clock signal; and a plurality of multiplexers coupled to the clock detector and to the PLL module. Each multiplexer is configured for receiving one pair of the plurality pairs of input clock signals and one pair of the at least one pair of reference clock signals, and selectively outputting, according to the protocol identifier, the pair of input clock signals and the pair of reference clock signals to drive a group of memory chips.