DIMM ECC Interleaving for 16-Bit Chipkill Protection
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Solution Overview
Problem
Existing chipkill schemes for memory devices, such as DIMMs, fail to provide adequate error protection and performance efficiency, especially when operating with 16-bit wide data buses, leading to increased latency and decreased error protection.
Innovation Solution
The implementation of an error correction and detection scheme using interleaved multibit symbols across multiple memory devices, which generates and encodes ECC data to correct and detect errors, allowing the memory module to function even if a constituent chip is damaged, and optimizing the bus width for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing chipkill schemes are applied to DIMMs with 16-bit wide chips, then the bus width is increased, but error protection capability deteriorates and latency increases
Solution Approach 1:
The patent segments the 16-bit data bus into multiple 4-bit groups, with each group processed by separate ECC circuits. This segmentation allows the system to maintain high bus width for productivity while providing comprehensive error protection across all segments, resolving the contradiction between bus width and error protection capability
Solution Approach 2:
The patent introduces a new dimension of error protection by implementing multi-level ECC coverage that operates independently across different bit groups. This dimensional approach to error correction allows the system to achieve both wide bus operation and robust error protection simultaneously
2Productivity
If existing chipkill schemes are applied to DIMMs with 16-bit wide chips, then the bus width is increased, but latency increases
Solution Approach 1:
By segmenting the ECC processing into parallel 4-bit group operations, the patent reduces the overall processing latency compared to sequential processing of the entire 16-bit bus. Each segment can be processed independently and simultaneously, maintaining high productivity while minimizing time loss
Solution Approach 2:
The patent merges multiple parallel ECC processing operations into a unified error correction framework, allowing simultaneous processing of multiple 4-bit groups. This combination of parallel operations reduces total latency while maintaining the high bus width needed for productivity
3Reliability
If interleaved multibit symbols are used across multiple memory devices, then error protection is enhanced, but device complexity increases
Solution Approach 1:
The patent segments the complex ECC encoding task into manageable 4-bit group operations that can be processed independently. This segmentation reduces the perceived complexity of the overall system while maintaining strong error protection across all memory devices through coordinated processing of segments
Data Source
AI summary
Symbols interleaved among a set of codewords can provide an error correction/detection capability to a dual in-line memory module (DIMM) with memory chips having a comparatively larger bus width. Data corresponding to a set of multibit symbols and received from one or more memory devices can be interleaved/distributed with other bits of at least one codeword.