DIMM Load Reduction via Dynamic Rank Remapping
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Solution Overview
Problem
Traditional DIMM-based memory systems face issues with high electrical loading on the system bus, limited operating frequency, and excessive power and heat concentration due to fixed rank configurations, which restrict the maximum operating frequency and require overdesigning of DIMM slots to handle peak power and heat.
Innovation Solution
The system re-maps RAM chips across available DIMMs, striping data words across multiple DIMMs to reduce electrical loading on byte lanes, using memory buffer circuits to route data bytes and control chip select signals, thereby minimizing the number of electrical loads on each byte lane.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If ranks are fixed in position on each DIMM, then the DIMM structure is simple and easy to manufacture, but the electrical loading on the system bus increases and the maximum operating frequency is limited
Solution Approach 1:
The patent implements dynamic rank remapping that allows the system to reconfigure which physical DRAM chips belong to which logical rank based on the number of populated DIMM slots. The host controller dynamically adjusts the mapping between byte lanes and DIMM slots, enabling the system to adapt its configuration rather than being fixed. This dynamic approach resolves the contradiction by allowing optimal electrical loading distribution while maintaining manufacturing simplicity.
Solution Approach 2:
The system changes the parameter of rank-to-DIMM mapping dynamically based on population count. When 1, 2, 3, or 4 DIMM slots are populated, different remapping schemes are applied to optimize the distribution of electrical loads across byte lanes. This parameter change allows the system to maintain maximum operating frequency by preventing excessive loading on any single byte lane, while the underlying DIMM structure remains simple and manufacturable.
2Use of energy by stationary object
If all power and heat is concentrated on a single DIMM when a rank is accessed, then the DIMM slot design must handle peak power, but this requires overdesigning external power delivery components
Solution Approach 1:
The patent segments the power and heat load distribution by remapping ranks across multiple DIMM slots. Instead of concentrating all power consumption for a single rank on one DIMM, the system distributes the electrical loads across multiple byte lanes and DIMM slots. This segmentation of power delivery paths prevents any single DIMM from bearing the full peak power burden, eliminating the need for overdesigned power delivery components while improving overall power distribution efficiency.
3Temperature
If continuous access is made to a single DIMM, then the DIMM must handle maximum heat dissipation continuously, but this requires each DIMM slot to be overdesigned for heat management
Solution Approach 1:
The patent segments thermal load distribution through dynamic rank remapping. By distributing logical ranks across multiple physical DIMM slots based on population, the system prevents continuous heat concentration on a single DIMM. When a logical rank is accessed, the physical DRAM chips are spread across multiple DIMM slots, thereby segmenting the heat generation and dissipation paths. This eliminates the need for each DIMM slot to be overdesigned for maximum heat dissipation while maintaining effective thermal management.
4Reliability
If DQS strobe signals are used to control contention on the DQ bus, then signal control is achieved, but various gaps and timing requirements complicate the system design
Solution Approach 1:
The patent implements dynamic byte lane assignment based on the number of populated DIMM slots. The host controller dynamically determines which byte lanes are active and assigns them to specific DIMM slots according to the current population configuration. This dynamic approach simplifies DQS strobe signal control by ensuring that active byte lanes have dedicated or properly shared paths, reducing contention and eliminating the need for complex gap timing adjustments. The system adapts its signal routing dynamically rather than requiring static complex timing control.
Data Source
AI summary
A load reduction system and method for use with memory systems which include one or more DIMMs, each of which includes a circuit arranged to buffer data bytes being written to or read from the DIMM, with the system nominally organized such that the bytes of a given data word are conveyed to the DIMMs via respective byte lanes and stored in a given rank on a given DIMM. The system is arranged such that the DRAMs that constitute a given rank are re-mapped across the available DIMMs plugged into the slots, such that a data word to be stored in a given rank is striped across the available DIMMs, thereby reducing the loading on a given byte lane that might otherwise be present. The system is preferably arranged such that any given byte lane is wired to no more than two of the DIMM slots.