Programmable DIMM Termination Resistance for Read/Write Matching
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Solution Overview
Problem
Existing memory systems face sub-optimal performance due to standard termination values for memory modules, which may not be optimal for specific DIMMs, leading to issues with signal integrity and power dissipation.
Innovation Solution
An interface circuit is used to select a single termination resistance value for memory modules based on resistance-setting commands from the memory controller, allowing for optimal on-die termination resistance that can differ between read and write operations, and can be chosen from a look-up table, thereby providing flexible and asymmetric termination values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard termination values are used for memory modules, then manufacturing and compatibility are simplified, but signal integrity and power dissipation performance deteriorate
Solution Approach 1:
The patent implements dynamic termination resistance selection by allowing the memory module to programmably configure termination resistance values based on operating conditions. The interface circuit receives resistance-setting commands from the memory controller and configures the termination resistance accordingly, enabling the system to adapt termination values for different signal integrity requirements rather than using fixed standard values.
Solution Approach 2:
The patent changes the termination resistance parameter from fixed standard values to programmable values. The memory module can be configured with different termination resistance values (e.g., 240 ohms, 120 ohms, 60 ohms, or other values) based on specific operating conditions, signal integrity requirements, and power dissipation considerations, allowing optimization beyond standard values.
2Ease of manufacture
If standard termination values are used for memory modules, then compatibility and ease of manufacture are improved, but power dissipation increases
Solution Approach 1:
The patent enables dynamic adjustment of termination resistance values to optimize power dissipation. The interface circuit can receive resistance-setting commands from the memory controller to configure appropriate termination resistance values during different operational phases (e.g., higher resistance during reads, lower resistance during writes), thereby reducing overall power dissipation compared to fixed standard values.
Solution Approach 2:
The patent allows changing the termination resistance parameter from fixed standard values to optimized programmable values. By selecting termination resistance values different from standard JEDEC-mandated values, the system can reduce power dissipation while maintaining signal integrity, particularly by using higher resistance values when signal quality is sufficient and lower values only when necessary.
3Device complexity
If a single termination resistance value is used for both read and write operations, then device complexity is reduced, but electrical performance deteriorates
Solution Approach 1:
The patent implements dynamic termination resistance configuration where the interface circuit can receive separate resistance-setting commands for read and write operations. The memory controller can program different termination resistance values for reads versus writes, allowing optimization of electrical performance for each operation type while maintaining manageable complexity through automated configuration.
Solution Approach 2:
The interface circuit serves multiple functions: it manages communication between the memory controller and memory circuits, and simultaneously configures termination resistance values based on received commands. This multi-functionality allows asymmetric termination values for reads and writes without significantly increasing overall device complexity, as the same interface circuitry handles both memory operations and termination configuration.
Data Source
AI summary
Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.