Dual-Channel DIMM Reconfiguration for Spare-Based Memory RAS

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High-end computing systems require a higher level of recoverability, availability, and serviceability (RAS) which is not met by standard dual channel memory systems optimized for lower end computer systems, leading to increased system costs due to the need for customized DIMMs.

Innovation Solution

A method and system that allows a dual channel DRAM DIMM optimized for lower end computer systems to be used as a single channel DIMM with a spare memory device, enabling higher RAS capabilities by configuring the memory controller to switch between dual and single channel modes, utilizing one ECC memory device for error correction and the other as a spare.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If dual channel memory mode is used, then memory bandwidth and performance are improved, but reliability and fault tolerance deteriorate due to lack of spare memory devices

Engineering Contradiction:
Improvememory bandwidthVSAvoidfault tolerance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The memory controller dynamically switches between dual channel mode (for performance) and single channel mode with spare (for reliability). The system can adapt its operational mode based on detected errors or failure conditions, allowing it to optimize between bandwidth and fault tolerance as needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the operational parameters of the memory system by reconfiguring the memory controller to operate in different modes. By changing parameters such as channel configuration and ECC protection scope, the system can transition between high-performance dual channel operation and high-reliability single channel operation with dedicated spare devices.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If single channel mode with spare is used, then reliability and fault tolerance are improved, but memory bandwidth and performance deteriorate

Engineering Contradiction:
Improvefault toleranceVSAvoidmemory bandwidth
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory controller dynamically switches between dual channel mode (for performance) and single channel mode with spare (for reliability). The system can adapt its operational mode based on detected errors or failure conditions, allowing it to optimize between bandwidth and fault tolerance as needed.

Inventive Principle:
Principle #15Dynamics

3Reliability

If customized DIMMs with spare devices are manufactured, then reliability is improved, but manufacturing cost and complexity increase

Engineering Contradiction:
Improvefault toleranceVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The invention makes standard dual channel DIMMs multi-functional by enabling them to operate in both dual channel mode (for performance) and single channel mode with spare (for reliability). This eliminates the need for separate customized DIMM designs, as a single standard DIMM can provide both operational modes through software/firmware control in the memory controller.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The memory controller dynamically switches between dual channel mode (for performance) and single channel mode with spare (for reliability). The system can adapt its operational mode based on detected errors or failure conditions, allowing it to optimize between bandwidth and fault tolerance as needed.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11037619B2Using dual channel memory as single channel memory with spares
Publication Date: 2021.06.15 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11037619B2 patent drawing
  • US11037619B2 patent drawing
  • US11037619B2 patent drawing

AI summary

A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a second ECC memory device protect the first memory devices and the second memory devices. The memory controller drives the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device, and the first ECC memory device protects the first memory devices and the second memory devices. The memory controller is configured to switch between the dual channel mode and the single channel mode.