DIMM Slot Test System Using Independent CPLD Boards
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Solution Overview
Problem
The existing boundary scan test systems for DIMM slots face instability due to serial connection through JTAG IN and JTAG OUT interfaces, leading to potential failures in testing.
Innovation Solution
A DIMM slot test system and method that eliminates series connection by using a test board with a TAP controller, CPU, and CPLD chips, where the CPU generates test signals in JTAG format, transmitting them through differential and IO pins to record test results independently for each DIMM slot without relying on serial connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If serial connection through JTAG IN and JTAG OUT interfaces is used for boundary scan test, then the test can be performed according to specification, but the line connection stability deteriorates due to long serial connection line
Solution Approach 1:
The patent divides the test system into independent test boards, each with its own CPU and JTAG interface. Each test board can independently test a DIMM slot without requiring serial connection through multiple boards. This segmentation eliminates the long serial connection line and improves line connection stability while maintaining the boundary scan test capability.
2Reliability
If serial connection through JTAG interfaces is used, then the boundary scan test can be performed, but the test stability deteriorates due to insufficient driving ability and stability of JTAG signal
Solution Approach 1:
The patent introduces differential pins as an intermediary transmission medium between the CPU and the DIMM slot. The differential signal transmission provides better signal integrity and immunity to noise, ensuring stable test results. The CPU generates test data and transmits it through differential pins to the specified test board, which then performs the boundary scan test on the DIMM slot.
Data Source
AI summary
A DIMM slot test system without series connection of test board through JTAG and a method thereof are disclosed. A DIMM connector interface of a test board is inserted to a DIMM slot of a circuit board under test, a CPU generates test data or a test signal based on a test signal with JTAG signal format, the CPU transmits test data to a specified CPLD chip through differential pins or IO pins, the specified CPLD chip records the received data as a test result; the CPU transmits the generated test signal to the specified CPLD chip, which then tests power pins or ground pins, reads and records values of the power pins or the ground pins as the test result; the CPU generates and transmits a test result read signal to the specified CPLD chip through the control pins, obtains the test result through data transmission pins.