Diode Aperture Electrode Structure for Simpler Semiconductor Fabrication
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Solution Overview
Problem
Existing semiconductor devices, such as transistors and diodes, require complex manufacturing processes and multiple steps, making them inefficient and costly to produce.
Innovation Solution
A diode and transistor structure utilizing a semiconductor layer with distinct regions of varying resistance, where a first insulating layer with aperture portions exposes the semiconductor layer, and conductive layers are connected to the semiconductor layer through these apertures, simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a diode is manufactured by connecting gate terminal and drain terminal of a common transistor, then the number of manufacturing steps is the same as for a transistor, but the device complexity increases due to the need for additional terminal connections
Solution Approach 1:
The invention extracts the gate terminal connection function by providing a dedicated connection structure between the gate terminal and drain terminal within the semiconductor device architecture, rather than requiring external wire bonding or additional connection steps. This integration reduces overall device complexity while maintaining manufacturing simplicity.
Solution Approach 2:
The invention merges the gate terminal and drain terminal functions into a unified structure where the gate electrode is directly connected to the drain region through the semiconductor layer, eliminating the need for separate connection steps and reducing device complexity.
2Reliability
If complex manufacturing processes are used for semiconductor devices, then device performance can be optimized, but production efficiency decreases and costs increase
Solution Approach 1:
The invention performs preliminary actions by pre-forming the gate electrode structure and its connection to the drain region during the main transistor fabrication process, rather than adding separate connection steps later. This integration maintains device performance while improving production efficiency.
Solution Approach 2:
The invention creates a multi-functional structure where the gate electrode serves both as the control terminal and as part of the drain connection path, reducing the number of manufacturing steps required while maintaining optimized device performance.
3Manufacturing precision
If multiple manufacturing steps are used for diode and transistor production, then device quality can be maintained, but production time and costs increase
Solution Approach 1:
The invention merges the diode and transistor manufacturing processes by using the same semiconductor layer structure and formation steps for both devices. The shared gate electrode structure and common fabrication steps reduce production time while maintaining manufacturing precision through consistent process parameters.
Solution Approach 2:
The invention segments the semiconductor device into standardized modules with common structures (semiconductor layer, gate electrode, insulating layers) that can be manufactured using identical process steps, then customized for specific device functions. This modular approach maintains quality through standardized processes while reducing overall production time.
Data Source
AI summary
A diode having a simple structure and a simple manufacturing method of the diode are provided. A diode including: a semiconductor layer having a first region and a second region having a resistance lower than a resistance of the first region; a first insulating layer having a first aperture portion and a second aperture portion and covering the semiconductor layer other than the first aperture and the second aperture, the first aperture portion exposing the semiconductor layer in the first region, the second aperture portion exposing the semiconductor layer in the second region; a first conductive layer connected to the semiconductor layer in the first aperture portion and overlapping with the semiconductor layer in the first region via the first insulating layer in a planar view; and a second conductive layer connected to the semiconductor layer in the second aperture.