Diode-Coupled Charge Storage Node for Flash Memory Scaling
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Solution Overview
Problem
1-transistor flash memory cells face limitations in scalability and reliability due to high operating voltages and degradation of thin tunnel oxide layers during programming and erasing processes.
Innovation Solution
The implementation of a memory cell structure that uses a diode with a charge storage node and a dielectric material between the channel region and the charge storage node, where charge is added or removed through the diode's insulator materials rather than the dielectric material, reducing operating voltages and minimizing tunnel oxide degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage (18-20V) is applied to program and erase the cell via tunneling through the tunnel oxide, then charge can be transferred to the floating gate for memory operation, but the ability to scale the memory cell is reduced and the tunnel oxide degrades over time
Solution Approach 1:
A charge storage node is introduced as an intermediary between the tunnel oxide and the floating gate. This intermediate structure allows charge to be transferred at lower voltages through the tunnel oxide, then stored in the charge storage node, and finally transferred to the floating gate when needed. This mediator approach eliminates the need for high voltage direct tunneling to the floating gate, reducing stress on the tunnel oxide and enabling better scaling.
Solution Approach 2:
The charge transfer process is segmented into two distinct stages: first, charge tunnels through the oxide to the charge storage node at low voltage; second, charge transfers from the charge storage node to the floating gate. This segmentation allows each stage to operate under optimal voltage conditions, with the tunneling stage using low voltage to preserve the oxide and the transfer stage using controlled voltage to populate the floating gate.
2Length of moving object
If the tunnel oxide layer is made thinner to improve scaling, then the memory cell can be scaled down, but the oxide layer degrades faster over multiple program/erase cycles
Solution Approach 1:
The charge storage node serves as a mediator that decouples the tunnel oxide thickness from the floating gate charging requirement. By introducing this intermediate storage node, the system can use thinner oxide layers for scaling while the charge storage node buffers the charge transfer process, preventing direct high-voltage stress on the thin oxide and thereby preserving its durability over multiple cycles.
3Reliability
If high voltage is used for programming and erasing, then charge transfer through the tunnel oxide is achieved, but power consumption increases
Solution Approach 1:
The charge storage node acts as an energy-efficient intermediary that enables charge transfer at lower voltages. By tunneling charge to the charge storage node at low voltage and then transferring it to the floating gate, the system avoids the high power consumption associated with direct high-voltage tunneling to the floating gate, thereby reducing overall power consumption while maintaining effective charge transfer.
Solution Approach 2:
The charge transfer process occurs in periodic stages: first tunneling to the charge storage node, then transferring to the floating gate. This periodic, two-stage approach allows the system to use low voltage for the energy-intensive tunneling operation and controlled voltage for the transfer operation, reducing peak power consumption compared to continuous high-voltage operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and enhances the scalability and reliability of memory cells by lowering operating voltages and minimizing dielectric material degradation, allowing for thinner dielectric layers and improved performance.
Implementation Method 1
biasing the diode with a first voltage to add charge to a charge storage node of a transistor through the diode, and biasing the diode with a second voltage to remove charge from the charge storage node through the diode. A first electrode of the diode is coupled to the charge storage node. Also, the first voltage and the second voltage are insufficient to provide the tunneling of charge through a dielectric material between the charge storage node and a channel region of the transistor.
Data Source
AI summary
Memory cell structures and methods are described herein. One or more memory cells include a transistor having a charge storage node, a dielectric material positioned between the charge storage node and a channel region of the transistor, the channel region positioned between a source region and a drain region, and a first electrode of a diode coupled to the charge storage node.