Diode With Deep Buffer Layer For Power Converter Loss Reduction

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Solution Overview

Problem

Existing diodes in power converters face challenges in reducing conduction and switching losses, suppressing surge voltage and high-frequency oscillations during reverse recovery switching, and maintaining dielectric strength while preventing leakage currents that can cause element breakdown or deterioration.

Innovation Solution

A diode structure is developed with a deep n-type buffer layer and a low carrier lifetime control layer, optimized to reduce carrier injection and decay speed, featuring a specific carrier concentration and thickness distribution that minimizes tail current and oscillations, and maintains dielectric strength through a high resistance peak in the low carrier lifetime control layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a sharp drop of electric current occurs during reverse recovery switching, then the switching speed is improved, but surge voltage and high-frequency oscillations are generated

Engineering Contradiction:
Improveswitching speedVSAvoidsurge voltage and oscillations
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

Different regions of the diode are given different doping concentrations to achieve different local characteristics. The first drift layer with higher doping concentration provides faster carrier decay for improved switching speed, while the second drift layer with lower doping concentration reduces tail current to suppress surge voltage and oscillations. This local quality differentiation resolves the contradiction between switching speed and noise generation.

Inventive Principle:
Principle #3Local quality

2Object-generated harmful factors

If the carrier lifetime is reduced to suppress tail current and oscillations, then noise is reduced, but the diode's ability to hold voltage in OFF state deteriorates

Engineering Contradiction:
Improvetail current and oscillationsVSAvoidvoltage holding capability
Core Design Contradiction:
Object-generated harmful factorsVSStrength

Solution Approach 1:

The drift layer is segmented into two regions with different doping concentrations that work together to resolve the contradiction. The first drift layer with higher doping concentration maintains the electric field for voltage blocking, while the second drift layer with lower doping concentration allows controlled carrier decay to reduce tail current. This segmentation enables both noise reduction and voltage holding capability to be maintained.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The diode structure achieves a tradeoff between conduction and switching losses, suppresses surge voltage and oscillations, and reduces leakage currents, ensuring reliable operation and maintaining dielectric strength.

Implementation Method 1

a deep n-type buffer layer and a low carrier lifetime control layer, optimized to reduce carrier injection and decay speed

Methodology Applied
Scientific EffectCarrier recombination:

Implementation Method 2

a high resistance drift layer that holds a high voltage in an OFF state makes it possible to reduce VF

Methodology Applied
Scientific EffectElectrical resistance: Electrical Resistance

Data Source

PatentEP3242330B1Diode and power convertor using the same
Publication Date: 2020.06.17 HITACHI POWER SEMICON DEVICE LTD
  • EP3242330B1 patent drawingFigure 1~2B
  • EP3242330B1 patent drawingFigure 3~4B
  • EP3242330B1 patent drawingFigure 5~6B

AI summary

A diode includes an anode electrode layer 600; a cathode electrode layer 500; a buffer layer 111 of a first conductivity type formed between the anode electrode layer 600 and the cathode electrode layer 500 in a region extending to a location at a distance of 30 µm or more from the cathode electrode layer 500; a first semiconductor layer 110 of the first conductivity type formed in a region between the anode electrode layer 600 and the cathode electrode layer 500, and being in contact with the buffer layer of the first conductivity type; and a second semiconductor layer 120 of a second conductivity type formed in a region between the anode electrode layer and the first semiconductor layer of the first conductivity type. The carrier concentration in the first semiconductor layer is lower than the carrier concentration in the buffer layer. The carrier concentration in the buffer layer is less than 1×1015 cm-3. Carrier injection from the cathode electrode layer into the first semiconductor layer is suppressed either by means of a low carrier lifetime control layer included in the buffer layer or by means of a further semiconductor region of the first conductivity type in a partial region between the cathode electrode layer and the buffer layer.