Diode-Based E-Fuse Cell for Miniaturization
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Solution Overview
Problem
Existing nonvolatile One Time Programmable (OTP) memory devices, such as e-fuse cells, face challenges with complex driving methods, low reliability, and large area requirements, which hinder the miniaturization of memory devices.
Innovation Solution
A semiconductor device design that incorporates a diode as a program selection device instead of a typical transistor, allowing for a different current path during program and read operations, reducing the area of the e-fuse cell and enabling stable operation with lower currents by using NMOS and PMOS transistors and a guard ring to enclose the e-fuse cell components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal fuse or polysilicon fuse is used as e-fuse with a program current of 10 to 30 mA, then the e-fuse can be blown to achieve programming, but a MOS transistor with a predetermined channel width is required to flow such high program current, thereby increasing the area of the e-fuse memory cell
Solution Approach 1:
The patent changes the electrical parameters of the e-fuse by using a silicide layer with controlled thickness and composition (e.g., cobalt silicide, nickel silicide, or titanium silicide) to reduce the program current requirement from 10-30 mA to a lower level, thereby reducing the transistor size and overall cell area while maintaining reliable programming
Solution Approach 2:
The patent employs composite material structures by combining silicon with various metal silicides (cobalt, nickel, titanium) to create an e-fuse structure that achieves both low resistance in the unprogrammed state and reliable programming at reduced current levels, thus reducing the required transistor channel width and cell area
2Reliability
If typical OTP memory devices using E-Memory or transistor are used, then nonvolatile memory functionality is achieved, but the driving method becomes complicated, reliability decreases, and area increases
Solution Approach 1:
The patent extracts the complex transistor-based switching mechanism from the e-fuse cell and replaces it with a simpler diode structure for selection, retaining only the essential NMOS transistors for current control, thereby simplifying the driving method while maintaining nonvolatile memory functionality and reliability
Solution Approach 2:
The patent uses a diode structure that is simpler and more reliable than transistor-based selection mechanisms, achieving the same selection function with fewer components and less complex control logic, thus reducing device complexity while maintaining reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces the area of the memory device, allowing for stable operation with lower currents and enabling miniaturization of memory devices by optimizing the arrangement of circuit devices in the e-fuse cell, specifically through the use of a diode for program selection and distinct current paths for program and read modes.
Implementation Method 1
a diode coupled to the first node and the first word line... A program current may pass through the first bit line, the second node, the e-fuse, the first node, the diode and the first word line, in that order
Implementation Method 2
The resistance before the program operation is about 50-100Ω, and as the program current flows through the e-fuse, e-fuse resistance after the program is more than such a few tens of Os of resistance
Data Source
AI summary
A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.