High Withstand Voltage Diode Impurity Profile Trade-off
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Solution Overview
Problem
Conventional diodes face challenges in adjusting the on-voltage and recovery loss trade-off characteristic due to variations in irradiation angle and temperature, leading to fluctuations in electrical characteristics and defects at high temperatures, especially with heavy metal diffusion or ion irradiation techniques.
Innovation Solution
A semiconductor device configuration with an n-type drift layer, multiple p-type anode layers with specific impurity concentrations and thicknesses, and n-type and p-type cathode layers, where the n-type cathode layer thickness is greater than or equal to the p-type cathode layer, allowing for adjustment of the on-voltage and recovery loss trade-off characteristic without life-time control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If life-time control using heavy metal diffusion or ion irradiation is used to adjust the VF-EREC trade-off characteristic, then the on-voltage and recovery loss can be adjusted, but variations increase depending on irradiation angle and temperature, and lattice defects occur causing electrical characteristic fluctuations and high-temperature defects
Solution Approach 1:
The patent removes the life-time control mechanism (heavy metal diffusion or ion irradiation) from the diode structure, eliminating the source of lattice defects and variability. The VF-EREC trade-off is adjusted instead through the geometric configuration of the cathode layers, specifically by controlling the thickness relationship between n-type and p-type cathode layers, thereby achieving parameter adjustment without the harmful side effects of irradiation-based methods
Solution Approach 2:
The patent changes the adjustment parameter from material-based life-time control to geometry-based cathode layer thickness control. By specifying that the n-type cathode layer thickness is equal to or larger than the p-type cathode layer thickness, the invention achieves VF-EREC optimization through dimensional parameters rather than material composition parameters, avoiding the variability associated with irradiation processes
2Ease of manufacture
If ion irradiation is used for life-time control, then the VF-EREC trade-off can be adjusted, but lattice defects change due to self-generated heat and electrical characteristics fluctuate
Solution Approach 1:
The patent extracts and eliminates the ion irradiation process from the manufacturing approach. Instead of using external energy input to modify material properties, the invention achieves VF-EREC adjustment through the inherent electrical characteristics of the multi-layer cathode structure with controlled thickness ratios, thereby avoiding self-generated heat and lattice defect formation
Solution Approach 2:
The invention transitions from process-based parameter control (ion irradiation dose, angle, temperature) to structure-based parameter control (cathode layer thickness ratios). This fundamental parameter change eliminates the coupling between manufacturing process variability and electrical characteristic stability, as the thickness ratio can be precisely controlled during fabrication without introducing lattice defects
3Reliability
If heavy metal diffusion or ion irradiation is used to adjust VF-EREC, then the trade-off characteristic can be modified, but defects occur in high-temperature operation due to large leak current from lattice defects
Solution Approach 1:
The patent removes the life-time control mechanism that introduces lattice defects, thereby eliminating the root cause of high-temperature leak current. The VF-EREC adjustment is achieved through the cathode layer thickness configuration, which modifies the electric field distribution and carrier injection characteristics without creating crystal lattice damage that would lead to thermal runout and increased leakage
Solution Approach 2:
The patent converts the traditional approach of using destructive irradiation methods into a beneficial geometric configuration approach. By controlling the n-type cathode layer to be thicker than or equal to the p-type cathode layer, the invention creates a structure that naturally optimizes the VF-EREC trade-off while simultaneously preventing the formation of leakage paths through defective lattice structures, thus turning a potentially harmful adjustment method into a beneficial defect-free design
Data Source
AI summary
It is an object of the present invention to provide a semiconductor device capable of adjusting a VF-EREC trade-off characteristic without a life-time control and a power conversion device having the semiconductor device. A semiconductor device according to the present invention includes a p−-type anode layer including a donor impurity and an acceptor impurity. An acceptor impurity concentration of the p-type anode layer is equal to or larger than a donor impurity concentration of the p−-type anode layer, an acceptor impurity concentration of the p−-type anode layer is equal to or larger than a donor impurity concentration of the p−-type anode layer, and a donor impurity concentration of the p−-type anode layer is equal to or larger than a donor impurity concentration of the n-type drift layer.