Diode-less OTP Memory Array Parasitic Current Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing one-time programmable (OTP) memory technologies face challenges in reducing parasitic current and increasing memory density, particularly as memory cell size decreases, and the turnaround time for manufacturing is lengthy due to the reliance on diodes and complex masking processes.
Innovation Solution
A diode-less OTP memory array is developed, incorporating a dielectric layer and fuse links between conductors to reduce parasitic current and improve memory density, with a manufacturing method that includes forming a three-dimensional inter-layered matrix using polysilicon or metal conductors and dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If diodes are used in OTP memory cells, then parasitic current is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent removes the diode component from the OTP memory cell structure entirely. By replacing the diode with a simple fuse link connected between bit line and word line, the invention extracts the harmful parasitic current issue from the system while eliminating the complex diode structure that caused manufacturing difficulties.
Solution Approach 2:
The invention changes the fundamental parameter of the memory cell structure by transitioning from a diode-based design to a fuse-link-based design. This parameter change eliminates the need for precise diode fabrication and reduces parasitic current through a simpler resistive fuse structure rather than a pn-junction diode.
2Quantity of substance
If memory cell size is reduced to increase density, then memory capacity increases, but parasitic current and manufacturing difficulty worsen
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell layouts to a three-dimensional inter-layered matrix structure. By stacking conductors and fuse links across multiple layers, the invention achieves higher memory density while maintaining larger effective cell dimensions that reduce parasitic current effects.
Solution Approach 2:
The invention segments the memory array into multiple layers with row conductors, column conductors, and fuse links distributed across different elevations. This segmentation allows independent optimization of each layer and reduces the parasitic current burden on individual cells while achieving high overall density.
3Reliability
If complex masking processes are used for programming, then OTP functionality is achieved, but turnaround time increases
Solution Approach 1:
The patent replaces the mechanical/chemical masking process with an electrical programming mechanism. Instead of using photomasks and chemical etching to program OTP cells, the invention uses electrical current to blow fuses, substituting a fast electrical process for a slow mechanical/chemical process and dramatically reducing turnaround time.
Solution Approach 2:
The invention uses simple fuse links as disposable programming elements rather than reusable masks. Each fuse link can be blown once to program the memory, eliminating the need for expensive, time-consuming mask fabrication and alignment processes while achieving reliable OTP functionality.
4Reliability
If diode structures are implemented, then memory programming is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent extracts the programming functionality from the complex diode structure and implements it through simple fuse links. This removal of the diode component simplifies the manufacturing process to basic conductor and fuse fabrication without requiring precise diode formation, junction control, or complex thermal processing.
Solution Approach 2:
The invention uses homogeneous conductor materials and simple fuse link structures throughout the memory array, eliminating the need for heterogeneous materials and complex processing steps required for diode fabrication. This homogeneity simplifies manufacturing while maintaining reliable programming capability through uniform fuse characteristics.
Data Source
AI summary
A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.