Optoelectronic Diode Matrix Growth via Dielectric Apertures
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Solution Overview
Problem
The fabrication process of optoelectronic devices with matrix-arrays of light-emitting diodes or photodiodes faces issues such as defects from localized etching, crystal quality degradation due to lattice parameter differences, and mechanical stress from thermal expansion mismatches, leading to performance degradation.
Innovation Solution
A process involving a growth substrate with a lower thermal expansion coefficient than the semiconductor stacks, a dielectric layer with an even lower expansion coefficient, and through-apertures for epitaxial growth of semiconductor stacks, which reduces the risk of crystal quality degradation and mechanical stress by avoiding localized etching and passivating lateral flanks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If localized etching is used to pixelate the diodes, then the diodes can be singulated and arranged in a matrix array, but defects are formed on the etched flanks which degrade diode performance
Solution Approach 1:
Instead of etching the semiconductor layers to create isolated diodes, the patent inverts the approach by growing the semiconductor stacks in isolation within through-apertures of a dielectric layer. This eliminates the harmful etching step while achieving the same pixelation effect, thereby preventing flank defects and improving diode reliability.
Solution Approach 2:
The patent introduces a dielectric layer with through-apertures as an intermediary structure during the epitaxial growth process. This dielectric layer acts as a mask and containment structure, enabling selective growth of semiconductor stacks in isolated regions without requiring subsequent etching, thus avoiding the creation of defective etched flanks.
2Ease of manufacture
If epitaxial growth is performed on a growth substrate, then semiconductor layers can be formed, but crystal defects such as threading dislocations form due to lattice parameter differences
Solution Approach 1:
The patent segments the epitaxial growth process by performing growth in isolated through-apertures rather than on a continuous substrate surface. This segmentation prevents the propagation of threading dislocations across the entire wafer, confining defects to localized regions and improving overall crystal quality in the active regions.
Solution Approach 2:
The patent applies local quality by creating isolated growth environments in each through-aperture, allowing each semiconductor stack to develop with optimized crystal quality in its specific region. The dielectric material surrounding each stack provides localized protection and control, improving the precision of crystal formation in each discrete location.
3Ease of manufacture
If cooling is performed after epitaxial growth, then the manufacturing process can be completed, but mechanical stress causes cracks or wafer bending due to thermal expansion differences
Solution Approach 1:
The patent explicitly addresses thermal expansion differences by selecting a dielectric layer material whose thermal expansion coefficient is matched to the semiconductor stack. This reduces the mechanical stress generated during cooling, preventing cracks and wafer bending while maintaining structural integrity throughout the manufacturing process.
4Reliability
If AlN interlayers or AlGaN gradients are inserted to engineer mechanical strain, then compressive strain can be introduced to counteract tensile stress, but the process complexity increases
Solution Approach 1:
The patent changes the fundamental parameter of stress management by selecting a dielectric material with appropriate thermal expansion properties, rather than introducing additional semiconductor layers for strain engineering. This parameter change achieves stress compensation through material selection alone, avoiding the complexity of inserting AlN interlayers or AlGaN gradients.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process improves the crystal quality and optical/electronic properties of the optoelectronic devices by reducing defects and mechanical stress, enhancing internal quantum efficiency and simplifying mechanical strain engineering.
Implementation Method 1
the difference in coefficient of thermal expansion between the growth substrate and the semiconductor stack, for example between the silicon of the substrate and the nitride-based semiconductor, may generate a high tensile mechanical stress in the semiconductor stack
Implementation Method 2
producing, by epitaxial growth, in the through-apertures and from the nucleation surface, the semiconductor stacks
Data Source
AI summary
A process for manufacturing an optoelectronic device having a diode matrix with semiconductor stacks involves providing a growth substrate having a support substrate coated with a nucleation layer defining a nucleation surface. A dielectric layer is deposited on the nucleation surface. A plurality of through-holes, extending to the nucleation surface, are formed in the dielectric layer. The nucleation layer, located in the through-holes, is etched to free up an upper surface of the support surface and expose a lateral surface of the nucleation layer forming a lateral nucleation surface. A dielectric region is formed extending in the support substrate such that, during a subsequent epitaxial growth stage, each first doped portion is formed especially from the lateral nucleation surface. In the through-holes and from the nucleation surface, the semiconductor stacks are epitaxially grown such that at least the first doped portions and active zones thereof are located in the through-holes.