Diode-Based M-ROM Fabrication for High-Density CMOS Integration
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Solution Overview
Problem
Conventional MOSFET and diode-based M-ROM technologies face challenges such as large cell size, high production costs, and integration issues with CMOS devices due to high thermal budgets, which hinder further density and reliability in semiconductor memory applications.
Innovation Solution
A diode-based M-ROM fabrication method involving epitaxial growth of monocrystalline silicon diodes with controlled doping and annealing processes, forming buried lines and isolation structures to reduce leakage current and enable high-density integration without compromising CMOS device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diode-based M-ROM is fabricated using conventional high-temperature annealing processes, then PN junction diodes can be formed, but the high thermal budget damages CMOS devices and decreases reliability
Solution Approach 1:
The patent changes the temperature parameter from conventional high-temperature annealing (850-900°C) to low-temperature annealing (400-600°C), enabling diode formation without damaging CMOS devices. This parameter change resolves the contradiction by achieving the necessary thermal processing while staying below the damage threshold for CMOS structures.
Solution Approach 2:
The patent replaces the conventional thermal annealing mechanism with a plasma-based processing mechanism. Plasma treatment enables impurity activation and diode formation at lower temperatures, substituting the high-temperature thermal field with a chemically active plasma field that achieves the same electrical property changes without thermal damage.
2Quantity of substance
If MOSFET-based M-ROM is used, then memory cells can be formed, but the cell size is large and further size shrinkage faces big challenges
Solution Approach 1:
The patent changes the fundamental device type parameter from MOSFET to PN junction diode, enabling smaller cell sizes. Diodes require fewer structural elements and can be densely packed compared to MOSFETs, directly addressing the cell size shrinkage challenge and enabling higher memory density.
3Reliability
If conventional high-temperature processing is used for diode formation, then PN junction diodes can be created, but the process time is long and production efficiency is low
Solution Approach 1:
The patent changes both temperature and time parameters simultaneously, using low-temperature (400-600°C) combined with plasma treatment to achieve rapid impurity activation. This parameter combination reduces processing time from conventional hours to minutes, dramatically improving productivity while maintaining diode formation quality.
Solution Approach 2:
The patent substitutes thermal diffusion mechanisms with plasma-enhanced processing mechanisms, enabling faster impurity activation and diode formation. The chemically active plasma species facilitate rapid electrical property changes at lower temperatures, reducing process time and increasing fabrication efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in a reliable, high-density M-ROM with reduced reverse leakage current and improved data integrity, compatible with CMOS processes, addressing the limitations of existing technologies.
Implementation Method 1
An epitaxial growth process is used to form a second layer on the first layer of the substrate
Implementation Method 2
performing an annealing process to activate the doped impurities
Data Source
AI summary
A mask read-only memory (M-ROM) device is provided. In an M-ROM device, a first layer having a first type doping is formed in a substrate. A plurality of buried lines is formed in the first layer of the substrate. The plurality of buried lines are arranged in parallel in a first direction and isolated from each other. An epitaxial growth process is used to form a second layer on the first layer of the substrate. A plurality of diodes is formed in the second layer. The plurality of diodes is arranged in an array. Each diode includes a first electrode having a second type doping and connecting with one of the plurality of buried lines, and a second electrode having a first type doping and located on the first electrode.