Diode Voltage Overshoot Calculation Method
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Solution Overview
Problem
High-speed interface integrated circuits face challenges with high voltage overshoots during electrostatic discharge (ESD) events due to the time it takes for carriers to establish conductivity modulation, leading to potential damage to gate oxides and requiring expensive and time-consuming iterative fabrication processes to achieve low voltage drops and parasitic capacitance in diodes.
Innovation Solution
A method is developed to calculate the maximum voltage overshoot based on diode parameters such as the length of the N region, current density, electron and hole mobility, doping concentration, and rise time of ESD events, allowing for the design of diodes with reduced voltage overshoots and low capacitance without the need for iterative fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diodes with lightly doped regions are used for ESD protection, then ESD protection capability is improved, but voltage overshoot increases causing potential damage to gate oxides
Solution Approach 1:
The patent applies parameter changes by modifying the doping concentration profile in the diode structure. Specifically, it uses a graded doping concentration that transitions from heavily doped contact regions to lightly doped drift regions, optimizing the balance between ESD protection capability and voltage overshoot control. This parameter optimization allows the diode to achieve low voltage drops during ESD events while maintaining acceptable voltage overshoot levels.
2Manufacturing precision
If iterative fabrication process is used to optimize diode parameters, then voltage drop and capacitance are improved, but development time and cost increase
Solution Approach 1:
The patent applies preliminary action by establishing analytical models and design guidelines before the fabrication process begins. The methodology includes calculating optimal doping concentrations, junction depths, and device dimensions using closed-form solutions that predict diode behavior during ESD events. This preliminary analytical work enables designers to optimize diode parameters on the first fabrication attempt, eliminating the need for multiple iterative fabrication cycles.
Solution Approach 2:
The patent replaces the mechanical/physical iterative fabrication process with an analytical calculation-based design approach. Instead of repeatedly fabricating and measuring diodes to optimize parameters, the invention uses mathematical models and closed-form solutions to directly determine optimal design parameters, substituting the trial-and-error fabrication process with a computational design methodology.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the design of diodes with controlled voltage overshoots and low capacitance, reducing the risk of failure and streamlining the development process by eliminating the need for costly and time-consuming iterative fabrication, ensuring reliable ESD protection for high-speed applications.
Implementation Method 1
the time it takes carriers to establish conductivity modulation
Data Source
AI summary
A method of designing a diode includes generating a layout of the diode and calculating a calculated voltage overshoot based on the layout. The calculating includes calculating variables of: the length of an N region of the diode; current density during an ESD event; electron charge; hole mobility; electron mobility; doping concentration of the diode; and rise time of the ESD event.