Diplexer Filter Circuit Layout to Reduce Shield-Induced Parasitic Capacitance
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Solution Overview
Problem
The proximity of an external shield electrode to a diplexer in a mobile terminal causes parasitic capacitance, leading to changes in the frequency of attenuation poles and degradation of filter characteristics in the diplexer.
Innovation Solution
The filter circuit is designed with an inductor of a resonant circuit positioned away from the upper surface of the dielectric substrate, reducing coupling with the external shield electrode, thereby minimizing the impact on filter characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the inductor is positioned close to the upper surface of the dielectric substrate for compact design, then the device size is reduced, but parasitic capacitance with the external shield electrode increases causing filter characteristic degradation
Solution Approach 1:
The patent positions the inductor in a dielectric layer between the upper and lower major surfaces of the dielectric substrate, utilizing the vertical dimension (depth) rather than only the horizontal plane. This three-dimensional placement allows the inductor to be compact while maintaining sufficient distance from the external shield electrode on the upper surface, thereby reducing parasitic capacitance without increasing device footprint.
Solution Approach 2:
The inductor is nested within the dielectric substrate structure, specifically placed in an internal dielectric layer rather than on the outer surface. This nesting approach embeds the inductor within the existing substrate architecture, achieving compact integration while isolating it from external electromagnetic interference and parasitic effects.
2Reliability
If the inductor is positioned away from the upper surface to reduce parasitic capacitance, then filter characteristics are improved, but the device occupies more vertical space
Solution Approach 1:
The solution utilizes the vertical dimension of the multilayer dielectric substrate to position the inductor in an internal layer, optimizing the balance between distance from the shield electrode and overall device height. This approach achieves reliable filter characteristics by reducing parasitic capacitance while maintaining compact vertical integration through efficient use of available dielectric layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains stable filter characteristics by reducing the influence of the external shield electrode, ensuring consistent performance of the diplexer.
Implementation Method 1
parasitic capacitance is generated between the shield electrode and an inductor included in a filter circuit in the diplexer
Implementation Method 2
a resonant circuit including an inductor and a capacitor... an attenuation pole generated by a resonant circuit including the inductor
Data Source
AI summary
A filter circuit is located in a dielectric substrate and includes multiple dielectric layers and a pass band in a range higher than a predetermined frequency. The dielectric substrate includes first and second major surfaces facing each other. External terminals for connection with an external device are on the second major surface. The filter device includes a first terminal, a second terminal, and first and second resonant circuits. The first resonant circuit is connected between the first and second terminals. The second resonant circuit is connected between the first resonant circuit and a ground potential. Each of the first and second resonant circuits includes an LC resonant circuit including a capacitor and an inductor. In the dielectric substrate, a portion of an inductor in the second resonant circuit is on or in a dielectric layer between the first major surface and inductors included in the first resonant circuit.