Dipole Dopant Patterning for Precise Transistor Threshold Voltage Tuning
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Solution Overview
Problem
There is a challenge in controlling and modulating the threshold voltage of transistors in semiconductor devices, particularly as gate lengths shrink, which affects the performance and efficiency of integrated circuits.
Innovation Solution
The method involves depositing a dipole dopant containing layer on a substrate, followed by a protective layer and a hardmask, and then using etching and annealing processes to diffuse the dipole dopant into the dielectric layer, allowing for precise adjustment of the threshold voltage by forming electrostatic dipole layers between dielectric layers and semiconducting films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to control threshold voltage, then manufacturing process is simpler, but threshold voltage modulation precision deteriorates
Solution Approach 1:
The substrate is divided into multiple regions with different dipole dopant configurations. Each region can be independently processed to achieve different threshold voltage characteristics, enabling precise local control while maintaining overall process manageability
Solution Approach 2:
Different regions of the substrate are given different dipole dopant types or concentrations to create localized threshold voltage adjustments. This allows each region to be optimized for its specific function while maintaining precision control
2Productivity
If gate length is reduced to improve device density, then IC performance improves, but threshold voltage control becomes more difficult
Solution Approach 1:
The dipole dopant concentration and type are adjusted as key parameters to maintain precise threshold voltage control in scaled devices. By changing these parameters across different regions, the invention enables continued precision control even as gate length decreases and device density increases
3Manufacturing precision
If dipole dopant is diffused into dielectric layer to adjust threshold voltage, then threshold voltage tuning precision improves, but process steps increase
Solution Approach 1:
The dipole dopant containing layer is deposited in advance before final device formation. This preliminary placement of dopants allows for controlled diffusion during subsequent annealing steps, achieving precise threshold voltage tuning while integrating the process into the existing manufacturing flow
Solution Approach 2:
A dipole dopant containing layer is introduced as an intermediary between the dielectric layer and subsequent processing steps. This intermediate layer enables precise threshold voltage control through controlled diffusion, while the layer itself can be removed or integrated into the final device structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables effective tuning of threshold voltage, enhancing the performance and efficiency of semiconductor devices by allowing for precise modulation of the voltage threshold, which is crucial for improved IC performance and cost reduction.
Implementation Method 1
annealing the substrate to diffuse the dipole dopant into a portion of the dielectric layer disposed in the first region
Implementation Method 2
annealing the substrate to diffuse the dipole dopant into a portion of the dielectric layer disposed in the first region
Implementation Method 3
exposing the substrate to an etchant to etch the hardmask and dipole dopant containing layer within the second region
Data Source
AI summary
A method of forming a structure on a substrate is provided. The method includes depositing a dipole dopant containing (DDC) layer including a dipole dopant on a first and second region of a dielectric layer (DL) of the substrate. A hardmask (HM) is deposited over the DDC deposited on the first and the second regions. A patterned photoresist layer (PR) is formed over the HM. The PR includes a first portion that is positioned over the first region and an opening that is positioned to expose a portion of the HM that is disposed over the second region of the substrate. The HM and DDC within the second region are etched and at least a portion of the DL is exposed within the second region. The PR is removed and the substrate is annealed to diffuse the dipole dopant into a portion of the DL disposed in the first region.