Multi-Threshold Voltage Devices Using Dipole-High Dielectric Combinations
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Solution Overview
Problem
Conventional methods for creating multi-threshold voltage (multi-Vt) semiconductor devices face challenges in scaling to smaller sizes due to the merging of thick work function metal stacks and increased variations in electron work function, which affect the reliability and mobility of transistors.
Innovation Solution
The method involves using thin dipole combinations, each comprising a dipole layer and a high dielectric constant layer, along with a work function metal layer, followed by a low temperature anneal, to shift the threshold voltage of transistors without increasing the overall stack thickness, thereby improving mobility and reliability at extreme scaled nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a thick work function metal stack is used to provide the desired range of threshold voltages, then the Vt tuning capability is improved, but the stack merges at lower spacings reducing device density
Solution Approach 1:
The patent divides the work function metal stack into multiple discrete layers (TiN layer, TaN layer, TiN layer, TiAlC layer, TiN layer) rather than using a single thick layer. This segmentation allows each layer to be precisely controlled in thickness, enabling Vt tuning without requiring excessive total thickness that would cause merging at scaled nodes.
Solution Approach 2:
The patent employs a composite structure combining multiple different metal materials (TiN, TaN, TiAlC) with distinct work function properties. This composite approach enables fine-grained control of the overall work function by adjusting the thickness and composition of each material layer, achieving the desired Vt range without increasing total stack thickness.
2Productivity
If the RMG spacing is decreased to achieve higher device density, then the device density is improved, but the work function metal stack merges and Vt control is lost
Solution Approach 1:
By segmenting the work function metal into multiple thin layers separated by intermediate layers, the patent reduces the effective thickness that would otherwise merge at smaller RMG spacings. This segmentation maintains distinct layer identities and functional control even when overall spacing is reduced for higher density.
Solution Approach 2:
The patent changes the physical parameters of the stack by introducing intermediate layers and adjusting the thickness of each component layer. This parameter optimization allows the stack to maintain functional integrity and Vt control at reduced spacings, enabling higher device density without loss of control precision.
3Ease of manufacture
If polycrystalline work function metals are used at lower sizes, then the manufacturing is simplified, but the random variations in electron work function increase
Solution Approach 1:
The patent uses a composite of multiple metal materials with different work function characteristics. This composite structure compensates for random variations in individual polycrystalline layers, as the overall work function is determined by the combined effect of multiple materials, reducing the impact of variations in any single layer.
Solution Approach 2:
The patent assigns different materials with specific work function properties to different positions within the stack. This local quality differentiation allows optimization of each layer's contribution to the overall work function, providing better control and reduced sensitivity to variations in individual polycrystalline layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the independent tuning of threshold voltages in transistors, enhancing performance and manufacturability by displacing defect bands in high dielectric constant layers, reducing the risk of aluminum-related issues, and maintaining effectiveness even at smaller device sizes.
Implementation Method 1
A first dipole combination is provided on a first portion of the components. The first dipole combination includes a first dipole layer and a first high dielectric constant layer on the first dipole layer
Implementation Method 2
a first high dielectric constant layer on the first dipole layer
Implementation Method 3
A low temperature anneal is performed after the step of providing the work function metal layer(s)
Data Source
AI summary
A method provides a gate structure for a plurality of components of a semiconductor device. The method provides a first dipole combination on a first portion of the components. The first dipole combination includes a first dipole layer and a first high dielectric constant layer on the first dipole layer. A second dipole combination is provided on a second portion of the components. The second dipole combination includes a second dipole layer and a second high dielectric constant layer on the second dipole layer. The first dipole combination is different from the second dipole combination. At least one work function metal layer is provided on the first dipole combination and the second dipole combination. A low temperature anneal is performed after the step of providing the work function metal layer(s). A contact metal layer is formed on the work function metal layer.