3D Dirac Energy Filter in Nanosheet Transistors for Steep Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional transistor technologies face challenges in voltage scaling due to thermal excitation in MOSFETs, leading to a subthreshold slope of at least 60 mV/decade, which hinders the reduction of steep-switching transistors' scaling.
Innovation Solution
The implementation of a three-dimensional (3D) Dirac energy filter formed from a 3D Dirac material in a steep-switching transistor, which operates as a Fermi-filter to exclude hot carriers and minimize rethermalization current, thereby reducing the subthreshold slope below 60 mV/decade.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional MOSFET structures are used, then device simplicity is maintained, but subthreshold slope is limited to at least 60 mV/decade due to thermal excitation
Solution Approach 1:
The patent employs a composite material structure combining 2D channel material (such as MoS2) with a 3D Dirac material energy filter (such as CoSi2). This composite structure enables the channel to maintain good interface quality while the Dirac material layer provides superior energy filtering capability, achieving subthreshold slope below 60 mV/decade by combining the advantages of different material systems.
Solution Approach 2:
The patent changes the material parameter from conventional silicon-based semiconductors to 3D Dirac materials with distinct electronic band structures. The Dirac material's linear dispersion relation and high carrier mobility enable enhanced energy filtering efficiency, fundamentally altering the transistor's electrical characteristics to achieve steep switching behavior with subthreshold slope below 60 mV/decade.
2Manufacturing precision
If energy filtering is implemented to reduce subthreshold slope, then switching precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts the energy filtering function from the main channel structure by introducing a separate 3D Dirac material layer positioned between the source/drain and the channel. This extracted filtering layer selectively removes hot carriers while maintaining the channel's primary transport function, achieving precise switching control without significantly complicating the overall device architecture.
Solution Approach 2:
The 3D Dirac material acts as an intermediary layer that mediates between the source/drain contacts and the channel. It selectively filters carriers based on their energy, allowing only low-energy carriers to pass through to the channel, thereby enabling precise switching control while maintaining a relatively simple overall device structure.
3Use of energy by moving object
If 3D Dirac energy filter is added, then power consumption is reduced through hot carrier filtering, but manufacturing complexity increases
Solution Approach 1:
The patent implements preliminary action by forming the 3D Dirac material energy filter layer before completing the source/drain contact formation. This sequencing allows the Dirac material to be deposited and patterned while the structure is still accessible, simplifying the overall manufacturing process compared to adding the filter layer after complete device assembly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D Dirac energy filter enables reduced power consumption and increased switching speeds by filtering out hot carriers and minimizing rethermalization current, thus overcoming the limitations of conventional transistors.
Implementation Method 1
The 3D Dirac material functions as an energy filter, also referred to as a Fermi-filter, that excludes hot carriers from entering the channel
Data Source
AI summary
A semiconductor structure includes a nanosheet stack on a substrate. The nanosheet stack has alternating layers of channel nanosheets and sacrificial nanosheets, which are formed between a first source/drain (S/D) region and a second S/D region. The semiconductor structure further includes a gate structure on the nanosheet stack, and a three-dimensional (3D) Dirac energy filter. The three-dimensional (3D) Dirac energy filter is formed on a portion of the substrate located in the first S/D region and includes a portion that contacts the nanosheet stack. A first S/D is on the 3D Dirac energy filter in the first S/D region, and a second S/D is on the substrate of the second S/D region.