3D Dirac Semimetal Inductor for RF IC Miniaturization
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Solution Overview
Problem
Conventional inductors in integrated circuits occupy significant space, making it difficult to miniaturize them while maintaining high inductance, and existing solutions like 2D graphene materials are not compatible with CMOS fabrication techniques and may not provide acceptable performance.
Innovation Solution
The use of 3D Dirac materials, such as Cd3As2, formed into geometric shapes like stripes or dots on a non-conductive substrate, which exhibit plasmonic resonance and kinetic inductance, allowing for ultra-compact inductor designs compatible with existing integrated circuit manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional inductor structures (coil windings around cores) are used, then inductance is achieved, but the inductor occupies significant space on the integrated circuit
Solution Approach 1:
The patent transitions from conventional planar inductor designs to three-dimensional Dirac material structures. By utilizing the unique electronic properties of 3D Dirac materials and forming geometric patterns (stripes, dots, rings) that exploit kinetic inductance in multiple dimensions, the inductor achieves higher inductance values within a smaller footprint area on the integrated circuit
Solution Approach 2:
The patent changes the material parameter from conventional conductors to 3D Dirac materials with exceptional kinetic inductance properties. This material parameter change enables the inductor to achieve the same or better inductance performance with significantly reduced physical dimensions, resolving the contradiction between footprint size and inductance performance
2Area of moving object
If 2D graphene materials are used to create inductors, then miniaturization is achieved, but compatibility with CMOS fabrication techniques is lost
Solution Approach 1:
The patent employs 3D Dirac materials that can be integrated with existing CMOS fabrication processes. These materials combine the desirable miniaturization properties of 2D materials with the manufacturing compatibility of bulk materials, allowing standard semiconductor fabrication techniques to be used while achieving compact inductor structures
Solution Approach 2:
The patent replaces the mechanical transfer and assembly processes required for 2D graphene materials with direct deposition and in-situ formation methods compatible with CMOS fabrication. This substitution eliminates the need for complex material transfer steps while maintaining the miniaturization benefits
3Reliability
If spiral conductive metallic wire traces are used, then inductance is achieved, but a large fraction of available space is consumed
Solution Approach 1:
The patent moves beyond planar spiral trace designs to three-dimensional Dirac material structures that exploit kinetic inductance effects in the vertical dimension as well. This dimensional transition allows the inductor to achieve comparable or superior inductance values with significantly reduced planar footprint area
Solution Approach 2:
The patent changes the fundamental material parameter from conventional metals to 3D Dirac materials, which possess exceptionally high kinetic inductance. This parameter change enables much higher inductance per unit area, resolving the contradiction between inductance value and circuit area occupation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of ultra-compact inductors with higher inductance and quality factors, reducing the footprint of inductors in integrated circuits while maintaining performance, and is compatible with current CMOS manufacturing techniques.
Implementation Method 1
The structure is capable of exhibiting plasmonic resonance, which arise from the large imaginary part of complex conductivity of such materials
Implementation Method 2
such structures are capable of serving as an inductor in an integrated circuit
Data Source
AI summary
Ultra-compact inductor devices for use in integrated circuits (e.g., RF ICs) that use 3-dimensional Dirac materials for providing the inductor. Whereas inductors currently require significant real estate on an integrated circuit, because they require use of an electrically conductive winding around an insulative core, or such metal deposited in a spiral geometry, the present devices can be far more compact, occupying significantly less space on an integrated circuit. For example, an ultra-compact inductor that could be included in an integrated circuit may include a 3-dimensional Dirac material formed into a geometric shape capable of inductance (e.g., as simple as a stripe or series of stripes of such material), deposited on a substantially non-conductive (i.e., insulative) substrate, on which the Dirac material in the selected geometric shape is positioned. Low temperature manufacturing methods compatible with CMOS manufacturing are also provided.