Direct Absolute Jump Instruction for Processor Branch Optimization

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Solution Overview

Problem

Indirect branches in processors have limitations such as less-than-ideal prediction behavior, lack of meaningful branch address calculation support, and increased costs due to misprediction and mis-speculation, particularly in cold code or large workload scenarios. Additionally, they pose security risks due to hijacking and reveal microarchitectural details.

Innovation Solution

The introduction of a direct absolute jump instruction (JMPABS/CALLABS) that allows for a 64-bit absolute target, enabling direct and unconditional jumps without relying on indirect branches. This instruction simplifies hardware logic, reduces branch mispredictions, and enhances security by reducing the attack surface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If indirect branches are used to jump anywhere, then the processor can achieve flexible branching, but branch prediction performance deteriorates and security vulnerabilities increase

Engineering Contradiction:

Improvebranching flexibilityVSAvoidbranch prediction accuracy

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent segments the branching mechanism into two distinct types: direct absolute jumps for precise targeting and indirect branches for flexible but controlled usage. This segmentation allows each mechanism to be optimized for its specific purpose, with direct jumps handling security-critical paths and indirect branches handling flexible but predictable transitions.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary mechanism (the direct absolute jump instruction) that mediates between the need for flexible branching and the need for secure, predictable execution. This intermediary provides a secure alternative for common branching scenarios, reducing reliance on indirect branches for security-sensitive operations.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If indirect branches are used for jumps, then the processor can handle any target address, but misprediction costs increase and performance decreases

Engineering Contradiction:

Improveaddress space coverageVSAvoidexecution speed

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent applies local quality by providing different branch mechanisms for different scenarios: direct absolute jumps for security-critical and performance-sensitive paths, and indirect branches for flexible but less critical paths. This localized optimization ensures that the most important paths execute at optimal speed while maintaining overall system flexibility.

Inventive Principle:

Principle #3Local quality

3Device complexity

If displacement limitation is placed on direct branches, then hardware complexity is reduced, but code flexibility is limited

Engineering Contradiction:

Improvehardware logic complexityVSAvoidbranch target range

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent segments the addressing capability into two paths: direct absolute jumps with full 64-bit addressing for security and performance, and indirect branches with displacement limitations for hardware simplicity. This segmentation allows the system to achieve both full addressing capability and hardware simplicity simultaneously by using the appropriate mechanism for each scenario.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS20250028532A1Direct, unconditional jump

Publication Date: 2025.01.23 INTEL CORP

AI summary

Techniques for performing an unconditional jump are described. In some examples, an instruction is processed to perform the unconditional jump. In some examples, the instruction is to at least include one or more fields for an opcode and a 64-bit bit immediate, wherein the 64-bit immediate is to encode an absolute address and the opcode is to indicate execution circuitry is jump to the absolute address.