Direct Backside Source/Drain Contacts for Scalable Nanowire Transistors
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits, particularly tri-gate transistors, is limited by variability in conventional fabrication processes, which hinders further reduction to the 10 nanometer node or below, and existing methods for backside power delivery in semiconductor devices complicate the process and increase cell area, leading to performance and layout constraints.
Innovation Solution
The implementation of direct backside source or drain contacts through increased source/drain depth and backside gate recess, combined with self-aligned access features, allows for simplified process flows and reduced parasitic capacitance, enabling efficient power delivery and reduced cell area by decoupling power and signal wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for multi-gate transistor scaling, then existing infrastructure compatibility is maintained, but manufacturing precision deteriorates at 10 nanometer node or below
Solution Approach 1:
The patent introduces backside contacts as a new dimensional approach to transistor fabrication. Instead of continuing to scale features on the front surface, the invention accesses source and drain regions from the backside of the substrate, creating a vertical/dimensional solution to the lateral scaling problem. This allows precise control of transistor dimensions at 10nm node while using established bulk silicon fabrication processes.
Solution Approach 2:
The fabrication process is segmented into distinct front-side and back-side operations. The front side handles gate and channel formation with high precision, while the back side handles source/drain contact formation. This segmentation allows each side to be optimized independently, maintaining manufacturing precision without increasing overall process complexity.
2Device complexity
If backside power delivery is implemented using existing methods, then power delivery function is achieved, but device complexity and cell area increase
Solution Approach 1:
The backside contacts serve multiple functions simultaneously: they provide both power delivery and signal routing capabilities. By making the source and drain regions accessible from the backside, the same contact structures can be used for both power supply and signal transmission, eliminating the need for separate power delivery infrastructure and reducing cell area.
Solution Approach 2:
The patent merges power delivery and signal routing into a single backside contact architecture. Instead of having separate front-side and back-side power delivery paths, the invention combines these functions into unified backside contacts that serve both purposes, thereby reducing overall device complexity and layout space requirements.
3Object-affected harmful factors
If source/drain depth is increased for direct backside contact, then parasitic capacitance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The backside contact structure is self-aligning through the substrate thickness. By accessing the source and drain regions from the backside at a controlled depth, the structure automatically achieves proper alignment without requiring additional alignment steps. This self-service mechanism reduces parasitic capacitance while maintaining manufacturing precision through inherent geometric constraints.
4Productivity
If multi-gate transistor dimensions are reduced, then device density is increased, but process constraints become overwhelming
Solution Approach 1:
Instead of continuing to reduce lateral dimensions of multi-gate transistors, the invention inverts the approach by accessing critical regions from the backside of the substrate. This inversion allows increased device density through vertical utilization of the substrate while avoiding the overwhelming process constraints that arise from extreme lateral scaling. The backside access method enables standard fabrication processes to achieve advanced node densities.
Data Source
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AI summary
Integrated circuit structures having direct backside source or drain contacts are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure over and electrically coupled to a corresponding conductive backside contact that extends laterally beyond the first epitaxial source or drain structure without contacting the first gate stack or the second gate stack. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin.