Direct-Bonded Capacitive Interconnects for Smaller Die Packages

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Solution Overview

Problem

Direct bonding and hybrid bonding processes in microelectronic devices often require critical tolerances and are hindered by the inclusion of large components like discrete capacitors, inhibiting size reduction and necessitating improved methods for coupling power, ground, and signal lines to enhance reliability and miniaturization.

Innovation Solution

Implementing capacitive couplings in a direct-bonded interface through a direct hybrid bonding process that creates a direct bond between dielectric surfaces and conductive interconnects, forming capacitors at the bonding interface for each signal line, allowing for very fine pitch and thinner dielectric layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If discrete capacitors are included in the package, then capacitance function is achieved, but package size increases

Engineering Contradiction:
Improvecapacitance functionVSAvoidpackage size
Core Design Contradiction:
ReliabilityVSVolume of moving object

Solution Approach 1:

The patent merges the capacitor function with the bonding interface structure by forming capacitive couplings between signal lines of first and second dies during the direct bonding process. This eliminates the need for separate discrete capacitors, achieving the capacitance function while reducing package size.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The bonding interface is designed to serve multiple functions simultaneously: it provides mechanical bonding between dies, electrical interconnection through conductive interconnects, and capacitive coupling for signal lines. This multi-functionality eliminates the need for separate capacitor components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If direct bonding process is used, then manufacturing yield improves, but critical tolerances are required

Engineering Contradiction:
Improvebond yieldVSAvoidtolerance
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent changes the electrical coupling parameter from direct conductive connection to capacitive coupling for signal lines. This parameter change allows the bonding interface to tolerate misalignment better, as capacitive coupling is less sensitive to positioning errors than direct metal-to-metal bonding, thereby reducing critical tolerances while maintaining high bond yield.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables smaller wafer-level packages, reduces material usage, and potentially lowers voltage requirements, facilitating the development of smaller microelectronic devices with improved reliability and manufacturing yield.

Implementation Method 1

A direct bonding process creates a direct bond between dielectric surfaces of two dies

Methodology Applied
Scientific EffectDielectric-to-dielectric direct bond:

Implementation Method 2

a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface

Methodology Applied
Scientific EffectMetal-to-metal direct bond:

Implementation Method 3

The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface

Methodology Applied
Scientific EffectCapacitive coupling: Capacitance

Data Source

PatentUS20260018564A1Capacitive coupling in a direct-bonded interface for microelectronic devices
Publication Date: 2026.01.15 ADEIA SEMICON TECH LLC
  • US20260018564A1 patent drawing
  • US20260018564A1 patent drawing
  • US20260018564A1 patent drawing

AI summary

Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface.