Direct-Bonded Chipset Interposer Layout for Lower Area and Power
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Solution Overview
Problem
Conventional chipsets face issues of large chip area and high power consumption due to the need for numerous connection interface circuits, which are exacerbated by the trend towards high-bandwidth and high-density chips.
Innovation Solution
The chipset design involves direct bonding of logic and input/output chips to an interposer using pad-to-pad connections with metal wiring, eliminating the need for additional connection interface circuits like D2D and HBM physical interface circuits, and utilizing a silicon interposer with deep trench capacitors and through silicon vias for signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection interface circuits (D2D interface circuit, HBM physical interface circuit) are set between logic chip and input/output chip, then signal transmission and data communication are enabled, but chip area increases and power consumption increases
Solution Approach 1:
The patent extracts and removes the intermediate connection interface circuits (D2D interface circuit, HBM physical interface circuit) from the system. By directly bonding the logic chip and input/output chip through pad-to-pad bonding, the intermediary components are eliminated, thereby reducing chip area while maintaining signal transmission capability through direct electrical connection.
Solution Approach 2:
The patent merges the connection function directly into the chip bonding structure. Instead of having separate interface circuits between chips, the bonding pads and interposer structure itself performs the connection function, combining the mechanical bonding and electrical connection into a single integrated structure that reduces overall chip area.
2Reliability
If connection interface circuits (D2D interface circuit, HBM physical interface circuit) are set between logic chip and input/output chip, then signal transmission and data communication are enabled, but power consumption increases
Solution Approach 1:
The patent extracts and removes the power-consuming intermediate connection interface circuits from the system. By eliminating the D2D interface circuit and HBM physical interface circuit, the sources of power consumption are removed, while signal transmission capability is maintained through direct pad-to-pad bonding with lower resistance and no intermediate processing stages.
3Adaptability or versatility
If additional connection interface circuits are added, then connectivity between logic chip and input/output chip is achieved, but device complexity increases
Solution Approach 1:
The patent extracts and removes the additional connection interface circuits (D2D interface circuit, HBM physical interface circuit) from the system architecture. By using direct pad-to-pad bonding, the complexity of multiple interface circuits is eliminated, while chip connectivity is achieved through the simplified direct bonding structure with fewer components and interconnections.
Data Source
AI summary
The present disclosure provides a chipset and a manufacturing method thereof. The chipset includes a logic chip, an input/output chip, and an interposer. The logic chip includes a plurality of first bonding components disposed in the first device layer. The input/output chip includes a plurality of second bonding components disposed in the second device layer. The interposer includes a plurality of third bonding components disposed in the third device layer. The logic chip is directly bonded to the first portion of the plurality of third bonding components of the interposer in a pad-to-pad manner through the first portion of the plurality of first bonding components, and the input/output chip is directly bonded to the second portion of the plurality of third bonding components of the interposer in a pad-to-pad manner through the plurality of second bonding components.