Direct Bonded Heterogeneous Integration Packaging Bridge
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Solution Overview
Problem
Conventional semiconductor packaging methods rely on interposers with through-silicon vias (TSVs), which complicate the design and increase latency due to longer wiring routes, limiting the development of thinner and larger structures with increased electrical communications.
Innovation Solution
The direct bonded heterogeneous integration packaging structure eliminates the need for an interposer layer and TSVs by using a bridge within a trench or pedestal on the packaging substrate, allowing direct electrical connections between chips, thereby reducing wiring complexity and enhancing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an interposer with through-silicon vias (TSVs) is used to provide high density interconnects, then electrical connections between chips are enabled, but wiring complexity increases and latency increases due to longer wiring routes
Solution Approach 1:
The patent extracts and eliminates the interposer layer from the packaging structure, allowing chips to be directly bonded together. This removal of the intermediate component simplifies the wiring architecture and reduces the number of interconnection layers needed, directly addressing the wiring complexity issue while maintaining electrical connection functionality through direct chip-to-chip bonding.
Solution Approach 2:
The patent transitions from a planar 2D interconnection approach (requiring interposers with TSVs for routing) to a vertical 3D direct bonding approach. By stacking chips vertically and bonding them directly face-to-face, the wiring path is dramatically shortened, reducing latency and complexity while maintaining high-density interconnects through the vertical dimension.
2Length of stationary object
If an interposer layer is used to provide high density interconnects, then electrical communications between chips are enabled, but the packaging structure becomes thicker and design flexibility is reduced
Solution Approach 1:
The interposer layer is completely removed from the packaging structure, eliminating the need for through-silicon vias and complex routing layers. This extraction reduces the overall packaging thickness and allows for more flexible die placement configurations, as chips can be directly bonded in various orientations and positions without being constrained by interposer routing patterns.
3Reliability
If conventional packaging methods with interposers are used, then electrical connections are established, but performance degradation occurs due to longer wiring routes and higher latency
Solution Approach 1:
The patent employs vertical 3D stacking with direct chip-to-chip bonding, replacing the horizontal 2D routing through interposers. This dimensional change creates direct vertical pathways for signal transmission, dramatically shortening the wiring routes and reducing signal latency while improving overall performance efficiency through closer proximity of interconnected chips.
Data Source
AI summary
Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.