Direct-Bonded Semiconductor Package for Fine-Pitch Pad Reliability
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving improved electrical characteristics and reliability on the front surface of semiconductor chips, particularly in miniaturization and high-performance applications.
Innovation Solution
A semiconductor package is designed with multiple semiconductor chips bonded directly through a process involving a conductive pattern, support insulating layer, and specific thermal expansion management, eliminating the need for conductive structures like bumps or solder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional bonding methods with conductive structures (bumps or solder) are used, then electrical connection is achieved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent removes the conductive bonding structures (bumps or solder) from the bonding interface entirely. The front pad of the first semiconductor chip is directly bonded to the back pad of the second semiconductor chip through direct pad-to-pad contact, eliminating the need for separate conductive interconnect elements and simplifying the overall bonding structure.
Solution Approach 2:
The patent merges the electrical connection function and mechanical bonding function into a single direct pad-to-pad contact interface. The front pad and back pad serve both as electrical conductors and as bonding surfaces, combining multiple functions into one integrated structure without requiring separate bonding materials.
2Length of moving object
If pad width is reduced for miniaturization, then device size decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary alignment and positioning of the semiconductor chips before the actual bonding process. The support insulating layer and front insulating layer are prepared with precise geometries that guide the alignment of pads, ensuring accurate positioning before bonding occurs and reducing the precision burden during the bonding step itself.
Solution Approach 2:
The patent introduces the support insulating layer as an intermediary structure between the device layer and front insulating layer. This intermediary layer provides mechanical support and defines precise geometric boundaries that facilitate accurate pad alignment, acting as a reference structure that enables miniaturization while maintaining alignment precision.
3Reliability
If thermal expansion is not managed, then manufacturing process is simpler, but bonding reliability deteriorates
Solution Approach 1:
The patent changes the physical and chemical parameters of the insulating layers through controlled annealing processes. The insulating layers are subjected to specific temperature ranges and durations to optimize their thermal expansion characteristics, ensuring they match or complement the semiconductor chips' thermal properties, thereby managing thermal stress without adding complex thermal management structures.
Solution Approach 2:
The patent explicitly accounts for and utilizes thermal expansion effects in the design and manufacturing process. By controlling the thermal history and composition of the insulating layers, the patent ensures that thermal expansion differences between layers are minimized or harmonized, preventing bonding failure while avoiding the need for complex compensation mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrical integration, reduces the width or pitch of pads, and improves thermal expansion support, leading to improved reliability and performance while enabling miniaturization.
Implementation Method 1
annealing and cooling a combination portion of the conductive pattern and the insulating material
Implementation Method 2
annealing and cooling a combination portion of the conductive pattern and the insulating material
Data Source
AI summary
A semiconductor package includes a plurality of semiconductor chips bonded to each other through direct bonding, the plurality of semiconductor chips including a first semiconductor chip and a second semiconductor chip. The first semiconductor chip including: a front insulating layer bonded to a back insulating layer of the second semiconductor chip; a front pad surrounded by the front insulating layer; a device layer on a back surface of the front insulating layer and including an interconnection structure electrically connected to the front pad; a conductive pattern between the interconnection structure and the front pad; and a support insulating layer between the device layer and the front insulating layer and surrounding the conductive pattern, wherein a gap is between a first side surface of the support insulating layer and a second side surface of the conductive pattern that faces the first side surface.