Direct Call Target Prefetching in Out-of-Order Processors

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Solution Overview

Problem

The performance of out-of-order processors is sensitive to the smooth supply of instructions, with instruction cache misses leading to performance degradation due to speculative code discard and inefficient branch prediction.

Innovation Solution

Implementing an Early Call instruction Fetch (ECAF) circuit that uses discarded branch predictor run-ahead to prefetch direct call targets, leveraging hardware modifications and ISA extensions to identify and prefetch call targets directly from instruction data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If branch predictor run-ahead is used to fetch speculative code, then instruction supply is improved, but performance degrades due to speculative code discard on misprediction

Engineering Contradiction:

Improveinstruction supplyVSAvoidperformance degradation

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

The patent converts the harmful effect of fetching speculative code that may be discarded into a beneficial prefetching mechanism. When the branch predictor mispredicts and speculative code is discarded, the ECAF circuit has already identified and prefetched the correct call target instructions, transforming the waste of speculative fetching into an opportunity for effective instruction prefetching without penalty.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

2Productivity

If early fetch of call targets is implemented, then cold instruction cache misses are reduced, but hardware complexity increases

Engineering Contradiction:

Improvecold instruction cache miss reductionVSAvoidhardware complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The ECAF circuit performs self-service by utilizing the existing branch predictor run-ahead mechanism and instruction decode pipeline to automatically identify call instructions and compute their targets. The circuit does not require external control signals or complex coordination with other pipeline stages, as it autonomously detects call opcodes, calculates target addresses, and triggers prefetching using readily available pipeline resources.

Inventive Principle:

Principle #25Self-service

3Speed

If branch predictor run-ahead is used, then instruction fetch efficiency is improved, but instruction level parallelism is reduced due to speculative code discard

Engineering Contradiction:

Improveinstruction fetch efficiencyVSAvoidinstruction level parallelism

Core Design Contradiction:

SpeedVSProductivity

Solution Approach 1:

The ECAF circuit performs preliminary action by identifying call instructions and computing their target addresses during the run-ahead phase, before the branch prediction is confirmed. This allows the correct call target instructions to be prefetched in advance and ready for execution when the misprediction is detected, maintaining instruction level parallelism by ensuring valid instructions are available without waiting for branch resolution.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentEP4625156A1Circuitry and methods for early fetch of call instructions

Publication Date: 2025.10.01 INTEL CORP

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AI summary

Techniques for early fetch of one or more call instructions are described. In certain examples, a hardware processor comprises a memory; an instruction fetch circuit to fetch an instruction from the memory for decode; a decoder circuit to decode the fetched instruction; and an early "call instruction" fetch circuit to determine that the instruction is a direct call, and in response to the instruction being the direct call, determine a target address for the direct call, and cause the target address to be sent to the instruction fetch circuit for a fetch of one or more instructions at the target address. In certain examples, the early call instruction fetch circuit is to determine that the instruction is the direct call based on an opcode of the fetched instruction.