Direct Chemical Plating for High-Aspect Ratio Interconnects
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Solution Overview
Problem
Conventional interconnect deposition techniques, such as damascene processes, face challenges in forming uniform conductive lines in vias or trenches of dielectric layers as integrated circuit sizes decrease, especially for high-aspect ratio structures, limiting their effectiveness.
Innovation Solution
The method involves forming a patterned seed layer over a semiconductor substrate, depositing metal lines using direct chemical plating, and applying a dielectric layer between adjacent metal lines, with optional barrier layers and planarization steps to create reliable interconnects and vias, allowing for the formation of metal structures in MOS devices and integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional damascene processes are used for interconnect deposition, then the process is well-established and reliable, but it becomes difficult to form uniform conductive lines in high-aspect ratio structures as integrated circuit size decreases
Solution Approach 1:
The patent replaces conventional physical vapor deposition (PVD) and chemical vapor deposition (CVD) processes with direct chemical plating (DCP). This substitution enables conformal deposition in high-aspect ratio structures by utilizing chemical reduction reactions that can uniformly deposit metal throughout deep trenches and vias, overcoming the limitations of line-of-sight deposition methods.
Solution Approach 2:
The patent changes the deposition mechanism from physical/chemical vapor phase processes to solution-phase chemical plating. By controlling parameters such as plating solution composition, temperature, and pH, the process achieves uniform metal deposition in high-aspect ratio structures that cannot be filled by conventional methods.
2Productivity
If integrated circuit size is reduced to continue scaling, then device density and performance improve, but the ability to form interconnects and vias using conventional techniques deteriorates
Solution Approach 1:
The patent replaces conventional PVD/CVD deposition techniques with direct chemical plating to enable interconnect formation in scaled devices. The chemical plating process can uniformly fill high-aspect ratio structures required by smaller device dimensions, maintaining manufacturability as circuits continue to scale.
Solution Approach 2:
The patent employs a seed layer formation step before the main metal deposition. This preliminary action creates a catalytic surface that enables subsequent chemical plating to proceed uniformly, ensuring successful interconnect formation in scaled devices where conventional methods would fail.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the deposition of uniform conductive lines and vias in dielectric layers, facilitating the formation of efficient interconnects and vias in MOS devices and integrated circuits, even in high-aspect ratio structures, thereby addressing the limitations of conventional techniques.
Implementation Method 1
selectively depositing metal lines over the seed layer by a process that includes direct chemical plating
Data Source
AI summary
A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.