Direct-Chip Attach Mainboard Assembly with Overlying Package
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Solution Overview
Problem
Hand-held computing devices face challenges in achieving a small form factor due to the increased height of package-on-package (PoP) components and limited routing flexibility caused by lower layer counts in substrates, which can also result in increased surface area when mounting packages side-by-side on the mainboard.
Innovation Solution
A system-level assembly where an integrated circuit (IC) die is directly attached to the mainboard with a package overlay, providing direct electrical communication and using a multi-layer substrate to increase routing flexibility without increasing the overall size or thickness, employing interconnects like solder bumps and underfill materials for mechanical and electrical attachment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If package-on-package (PoP) architecture is used to reduce surface area, then the overall height (or thickness) of the assembly increases
Solution Approach 1:
The patent implements a nested configuration where the first package is positioned directly over the second package, and the third package is positioned directly over the first package, creating a vertical stack. This nesting arrangement consolidates multiple IC packages into a compact vertical structure, minimizing the surface area footprint while maintaining all necessary functional components.
Solution Approach 2:
The patent transitions from a horizontal side-by-side package arrangement to a vertical stacked configuration. By utilizing the vertical dimension (Z-axis) instead of horizontal expansion, the design achieves three-dimensional packaging that reduces the X-Y plane footprint while managing height through optimized package thickness and interconnect structures.
2Area of stationary object
If package-on-package (PoP) architecture is used to reduce surface area, then routing flexibility is limited due to lower layer count in the lower substrate
Solution Approach 1:
The patent divides the interconnection system into multiple independent substrates, each with their own layer structures and routing capabilities. The first substrate, second substrate, and third substrate are segmented as separate entities with distinct routing paths, allowing complex signal distribution to be achieved across multiple layers without requiring a single high-layer-count substrate.
Solution Approach 2:
The nested package structure enables multiple routing planes at different vertical levels. Signals can be routed within individual packages and between packages through controlled interconnect structures, creating a multi-level routing architecture that compensates for the limited layer count in any single substrate.
3Length of stationary object
If packages are mounted side-by-side on the mainboard to avoid increased height, then the surface area of the assembly increases
Solution Approach 1:
The patent utilizes vertical stacking in the Z-dimension to accommodate multiple IC packages, transforming a two-dimensional horizontal layout into a three-dimensional structure. This dimensional transition allows packages to be arranged vertically rather than horizontally, thereby reducing the surface area footprint while maintaining acceptable height through optimized package thickness.
Solution Approach 2:
The nested configuration places packages directly over one another in a vertical stack, with the first package over the second and the third package over the first. This nesting arrangement consolidates the physical footprint of multiple packages into a compact vertical column, minimizing the horizontal space required on the mainboard.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a compact form factor with enhanced routing flexibility and reduced thickness, maintaining a small footprint while providing efficient electrical communication between components, thus addressing the limitations of traditional PoP architectures.
Implementation Method 1
employing interconnects like solder bumps and underfill materials for mechanical and electrical attachment
Implementation Method 2
employing interconnects like solder bumps and underfill materials for mechanical and electrical attachment
Data Source
AI summary
Disclosed are embodiments of a system-level assembly including an integrated circuit (IC) die directly attached to a mainboard. An IC die directly attached to a mainboard or other circuit board may be referred to as a direct-chip attach (DCA) die. A package is disposed over at least a portion of the DCA die and coupled with the mainboard. The package includes one or more other IC die disposed on a substrate. Other embodiments are described and claimed.