Direct Chip Bonding Structure for Smaller WL-CSP Packages
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Solution Overview
Problem
In semiconductor devices with a Wafer Level Chip Size Package (WL-CSP) structure, the use of wire bonding or through electrodes leads to increased chip size, making it difficult to downsize the package.
Innovation Solution
A semiconductor device structure featuring a first semiconductor chip with metal terminals and a bonding layer, a second semiconductor chip mounted on the first with oxide-filled bonding layers for direct Cu-Cu connections, and a post electrode and burying layer to reduce chip size, along with a manufacturing method that includes steps for mounting, processing, and forming these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding or through electrode is used to connect upper and lower chips, then reliable electrical connection is achieved, but chip size increases making it difficult to downsize the package
Solution Approach 1:
The invention extracts and eliminates the wire bonding and through electrode components from the chip stacking structure. By directly bonding the bonding pads of the first chip to the bonding pads of the second chip through oxide film formation and direct contact, the patent removes the intermediate connection elements that previously increased chip size, thereby achieving package downsizing while maintaining electrical connection reliability.
Solution Approach 2:
The invention merges the bonding pad regions of the first and second chips into a single integrated bonding interface. By forming oxide films on the bonding pads and directly bonding them together, the patent combines what were previously separate components (wire bonds or through electrodes) into a direct chip-to-chip connection, reducing overall package area while ensuring reliable electrical connection.
2Area of moving object
If direct chip-to-chip bonding is implemented without wire bonding or through electrodes, then chip size is reduced, but manufacturing complexity increases
Solution Approach 1:
The invention applies local quality by forming oxide films specifically on the bonding pad regions rather than across the entire chip surface. This localized oxide formation simplifies the manufacturing process compared to comprehensive surface treatment, while still enabling direct bonding at the critical connection points, thus reducing chip size without significantly increasing manufacturing complexity.
Solution Approach 2:
The invention employs preliminary action by pre-forming oxide films on the bonding pads before the direct bonding process. This preparatory step simplifies the subsequent bonding operation, as the oxide films are already in place to facilitate direct contact between chips, thereby reducing overall manufacturing complexity despite the novel direct-bonding approach.
3Reliability
If oxide film is used to fill between metal terminals and external metal terminals, then bonding reliability is improved, but manufacturing steps increase
Solution Approach 1:
The oxide film serves multiple functions simultaneously: it provides reliable bonding between metal terminals, acts as a filling material to level the surface, and creates a stable interface for direct chip-to-chip connection. By consolidating these multiple functions into a single material layer, the invention improves bonding reliability without proportionally increasing manufacturing steps, as the oxide formation process achieves several objectives in one operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables chip size reduction with a simple structure by achieving direct connections between chips, facilitating efficient processing and packaging while allowing for adequate coverage and mounting of thin core chips on base chips.
Implementation Method 1
The bonding layer includes an oxide film provided on the one surface to fill between the plurality of first metal terminals and the plurality of external metal terminals
Implementation Method 2
The second semiconductor chip is mounted on the first semiconductor chip by bonding the bonding layers one another such that the respective plurality of second metal terminals contact the respective plurality of first metal terminals
Data Source
AI summary
A semiconductor device includes a first semiconductor chip, a second semiconductor chip, a post electrode, and a burying layer. The first semiconductor chip includes a plurality of first metal terminals and external metal terminals formed in different regions, and a bonding layer including an oxide film to fill therebetween. The second semiconductor chip includes a plurality of second metal terminals formed on an opposed surface of the first semiconductor chip and a bonding layer including an oxide film provided to fill therebetween. The second semiconductor chip is mounted on the first semiconductor chip by bonding the bonding layers one another. The post electrode is formed above the one surface of the first semiconductor chip and provided on the external metal terminal of the first semiconductor chip. The burying layer buries the second semiconductor chip and the post electrode on the one surface of the first semiconductor chip.