Direct Code Execution from Block-Based Memory

The patent divides the block-based memory into smaller sub-blocks or pages that can be individually accessed and cached. This segmentation allows the system to retrieve only the necessary code portions needed for execution rather than requiring entire blocks to be transferred, thereby enabling direct code execution from block-based memory without needing additional complex memory structures.

The patent introduces a cache memory as an intermediary between the block-based NAND flash memory and the processor. This cache serves as a buffer that stores recently accessed code blocks, allowing the processor to execute code directly from the cache while the underlying storage remains block-based. This intermediary structure enables XIP capability without fundamentally changing the block-based memory architecture.

The patent implements error detection and correction mechanisms that operate preliminarily on data before it is cached or executed. Error correction codes (ECC) are applied to data blocks during the caching process, and validation checks are performed before code execution. This preliminary error handling ensures that cost-effective block-based memory can be used while maintaining high reliability through proactive error management.

The patent incorporates feedback mechanisms where the system continuously monitors for errors in block-based memory operations. When errors are detected during code execution or data retrieval, the system automatically triggers error correction routines and can invalidate corrupted cache entries. This feedback loop ensures that cost-effective block-based memory maintains reliable operation through continuous error monitoring and correction.

The patent merges the cache memory functionality with the block-based memory controller into a single integrated unit. Rather than using separate off-chip memory for buffering, the system combines the caching function with the existing memory controller that manages block-based memory operations. This integration enables direct code execution while maintaining a compact, cost-effective design without requiring additional discrete memory components.

The patent makes the memory controller multi-functional by enabling it to perform both block management and caching operations. The same controller that handles block-based memory access also manages the cache memory, performing data retrieval, caching, and error correction functions. This universal approach enables direct execution capability without requiring dedicated separate memory structures, thereby improving integration and reducing cost.