Direct Contact Interconnect Substrate for High-Density PCB Packaging
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Solution Overview
Problem
Current methods for manufacturing molded core substrates are limited in their ability to achieve high-density interconnects and efficient processing, particularly in semiconductor assemblies, where they often require large capture pads and deformable insulting layers that complicate the manufacturing process and increase costs.
Innovation Solution
The method involves forming a molded core substrate with alternating conductive and dielectric layers, using unit-specific patterning and Adaptive Patterning techniques to eliminate the need for large capture pads, and employing a mold compound with a low k dielectric and fillers to reduce warpage and enhance thermal management, while incorporating tracking identifiers for process control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional molded core substrate methods are used with large capture pads and deformable insulting layers, then electrical connections can be established, but manufacturing complexity increases and processing efficiency decreases
Solution Approach 1:
The patent removes the deformable insulting layer and large capture pads from the traditional substrate structure, extracting the problematic elements that caused manufacturing complexity while maintaining electrical connection functionality through direct contact interconnects
Solution Approach 2:
The invention changes the physical parameters of the substrate by using a rigid core instead of deformable materials, and by reducing the size of contact areas from large capture pads to small direct contact interconnects, thereby simplifying the manufacturing process
2Quantity of substance
If unit-specific patterning and Adaptive Patterning techniques are employed to eliminate large capture pads, then substrate density increases, but manufacturing precision requirements increase
Solution Approach 1:
The substrate is divided into multiple processing stages with conductive layers and dielectric layers formed separately and alternately, allowing precise control of each layer while achieving high overall density through systematic segmentation of the manufacturing process
Solution Approach 2:
The patent transitions from planar patterning to three-dimensional layering by forming alternating conductive and dielectric layers, enabling high-density interconnects through vertical stacking while maintaining manufacturing feasibility
3Stability of the object's composition
If mold compound with low k dielectric and fillers is used, then warpage is reduced and thermal management is enhanced, but material complexity increases
Solution Approach 1:
The patent employs a composite mold compound containing low k dielectric materials and fillers that provides both mechanical stability to reduce warpage and thermal management capabilities, accepting material complexity as necessary to achieve multiple performance benefits simultaneously
4Reliability
If tracking identifiers are incorporated for process control, then manufacturing reliability improves, but substrate complexity increases
Solution Approach 1:
Tracking identifiers are introduced as intermediary elements that facilitate process control and reliability monitoring without becoming integral functional parts of the substrate, allowing reliable manufacturing while maintaining substrate simplicity for its primary electrical function
Data Source
AI summary
The disclosure concerns method of making an interconnect substrate that may comprise providing a core. The core may comprise a composite core, which may comprise a PCB, a laminate core with build-up layers, or molded core. A first patterned frontside conductive layer may be formed over a front side of the core. A first frontside molded dielectric layer may be disposed over the front side of the core and over the first patterned frontside conductive layer. One or more other dielectric layers (such as polyimide) may be disposed before (and under) the first frontside molded dielectric layer. The core may be flipped such that a back side of the core is presented or configured for processing. A first patterned frontside conductive layer may be formed over the back side of the core.