Multi-Core Cache Eviction via Direct Core-to-Core Transfers
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Solution Overview
Problem
Existing multi-core processors face inefficiencies in evicting cache lines from lower-level caches to higher-level caches, often requiring multiple transfers through a cache manager circuit, which increases power consumption and interface congestion.
Innovation Solution
The solution involves direct core-to-core transfers of evicted cache lines from a source CPU core to a target CPU core for storage in a slice of the higher-level cache memory, bypassing the cache manager circuit for reduced transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If cache lines are evicted through the cache manager circuit, then data coherence is maintained, but the number of transfers increases causing higher power consumption and interface congestion
Solution Approach 1:
The patent extracts the cache line transfer operation from the centralized cache manager circuit and relocates it to direct peer-to-peer transfers between caching agents. This removes the intermediary component (cache manager) from the transfer path, reducing the number of transfers and associated power consumption while maintaining coherence through selective involvement of the cache manager only when necessary
Solution Approach 2:
Caching agents are empowered to perform evictions autonomously by directly transferring cache lines to other caching agents without requiring cache manager intervention. Each caching agent serves itself by managing its own cache line evictions through direct transfers, reducing overall system complexity and power consumption
2Ease of operation
If cache lines are evicted through the cache manager circuit, then coherence management is centralized, but interface congestion increases
Solution Approach 1:
The patent extracts the bulk of cache line transfer traffic from the centralized cache manager interface and redirects it to direct peer-to-peer interfaces between caching agents. This reduces interface congestion on the cache manager while distributing the transfer load across multiple direct connections
Solution Approach 2:
The patent segments the centralized cache management function into distributed peer-to-peer transfer operations. Instead of all cache lines flowing through a single cache manager interface, the system divides transfers into direct segmented paths between specific caching agents, reducing congestion on any single interface
Data Source
AI summary
To reduce a number of cache line transfers in a multi-core processor that includes a cache manager circuit to manage coherence of a cache memory system, a source central processing unit (CPU) core that is evicting a cache line from an associated lower-level cache memory transfers the evicted cache line to another core for storage in a “slice” of a higher-level cache memory associated with the other core, rather than to the cache manager circuit. In some examples, the cache manager circuit receives a request for the eviction, determines which CPU core will store the target CPU core for the evicted cache line, and notifies the source CPU core of the identification of the target CPU core. In some examples, the cache manager circuit informs the target CPU core that the evicted cache line will be transferred.