Direct Data Transfer Circuit for Memory Subsystem Bottlenecks
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Solution Overview
Problem
In systems comprising a processor and a memory circuit, data transfers between memory circuits often require significant processor involvement, leading to inefficiencies due to the need for data manipulation and reorganization, which can slow down operations and burden data exchange channels.
Innovation Solution
A system with a direct data transfer circuit that receives specific instructions from an external processor to control data transfers between memory circuits, utilizing sub-region definitions and relative coordinates to execute multiple transfers efficiently, reducing processor load and optimizing data exchange by rearranging data during transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data transfers between memory circuits are controlled by the processor through read/write operations, then data manipulation and reorganization can be performed, but processor workload increases and data exchange channels become burdened
Solution Approach 1:
A direct data transfer circuit is introduced as an intermediary component between memory circuits. This circuit receives specific instructions from the processor and autonomously controls data transfers, including manipulation and reorganization operations, without requiring continuous processor intervention. The circuit acts as a mediator that handles complex data transfer tasks independently, relieving the processor from burdened data exchange channels.
Solution Approach 2:
The direct data transfer circuit is designed to autonomously perform data manipulation and reorganization operations based on specific instructions. Once configured with parameters such as source/destination addresses, transfer patterns, and reorganization rules, the circuit self-manages the entire data transfer process including reading from source memory, manipulating data according to predefined patterns, and writing to destination memory without requiring processor involvement in each operation.
2Productivity
If multiple successive transfer instructions are executed towards or from the same sub-region, then data exchange efficiency improves, but instruction decoding and execution complexity increases
Solution Approach 1:
The direct data transfer circuit is pre-configured with a sub-region definition that identifies a specific area in the source or destination memory. This preliminary action of defining the sub-region allows multiple successive transfer instructions to operate within the same contextual framework, eliminating the need for repeated full address decoding and reducing execution complexity while maintaining high data exchange efficiency.
Solution Approach 2:
The direct data transfer circuit is designed with universal functionality to handle multiple successive transfer instructions within a defined sub-region. The circuit can execute various transfer patterns (sequential, interleaved, transposed, etc.) and manipulation operations within the same sub-region context, making it a multi-functional device that reduces overall system complexity despite handling diverse transfer scenarios.
Data Source
AI summary
The present description concerns a system comprising a processor and an SDMA circuit of direct transfer of a data sequence between a source memory circuit and a destination memory circuit, a sub-region of the source circuit comprising the elements of a data array, the SDMA decoding computing kernel information called BIT_PATTERN of an elementary data pattern to be transferred defined from an elementary array having a predefined size smaller than the size of said data array and intended to identify an elementary array window of said array, each element of the elementary array comprising a bit capable of taking a state “1” or “0” according to whether the element belongs or not to said pattern, the SDMA recovering the data of said array associated with elements of the BIT_PATTERN having their bit at “1”.