Direct Decision Feedback Equalization for Memory Subsystems

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Solution Overview

Problem

Existing data transmission systems in memory sub-systems face challenges with high-speed data processing due to limitations in equalization techniques, particularly with linear equalizers generating signal noise and producing inaccurate sample estimations.

Innovation Solution

Implementing a direct decision feedback equalization (DFE) mode using a direct DFE that includes multiple data detectors with respective reference voltages, eliminating the need for dedicated offset correction circuitry and capacitive circuitry in the signal path.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If linear equalization is used for high-speed data transmission, then data rate can be increased, but signal noise is generated and sample estimation accuracy deteriorates

Engineering Contradiction:
Improvedata rateVSAvoidsample estimation accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The equalization process is divided into two separate functions: a feedforward equalizer that processes the incoming signal and a decision feedback equalizer that uses previously detected symbols to correct residual interference. This segmentation allows each component to specialize in reducing specific types of distortion without generating excessive noise, thereby maintaining sample estimation accuracy while supporting high data rates

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The decision feedback equalizer uses a feedback mechanism where previously detected symbols are fed back through a feedback filter to generate an estimate of post-cursor interference, which is then subtracted from the current symbol estimate. This feedback loop continuously improves estimation accuracy by eliminating residual intersymbol interference that the feedforward equalizer cannot remove, solving the accuracy deterioration problem while maintaining high data rate capability

Inventive Principle:
Principle #23Feedback

2Measurement precision

If dedicated offset correction circuitry and capacitive circuitry are added to improve equalization accuracy, then sample estimation accuracy is improved, but device complexity and signal path length increase

Engineering Contradiction:
Improvesample estimation accuracyVSAvoidcircuitry complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The offset correction function is merged into the decision feedback equalizer structure itself, where the feedback filter coefficients automatically compensate for offset errors. This integration eliminates the need for separate dedicated offset correction circuitry, reducing device complexity while maintaining or improving sample estimation accuracy through the unified equalization process

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The decision feedback equalizer performs multiple functions simultaneously: it reduces pre-cursor and post-cursor intersymbol interference, corrects offset errors, and improves sample estimation accuracy all within a single circuit structure. This multi-functionality eliminates the need for separate specialized circuitry for each function, thereby reducing overall device complexity while achieving high estimation accuracy

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250061925A1Direct decision feedback equalization single-ended receiver
Publication Date: 2025.02.20 MICRON TECHNOLOGY INC
  • US20250061925A1 patent drawing
  • US20250061925A1 patent drawing
  • US20250061925A1 patent drawing

AI summary

A system including a memory sub-system controller to transmit a data signal via a communication channel. The system includes a receiver to receive the data signal from the memory sub-system controller via an interface, the receiver comprising a decision feedback equalizer (DFE) sub-system. The DFE sub-system includes a first data detector circuit including a first tap circuit, where the first data detector circuit generates, using a first reference voltage, a first subset of detected values corresponding to the data signal. The DFE sub-system includes a second data detector circuit including a second tap circuit, where the second data detector circuit generates a second subset of detected bit values corresponding to the data signal using a second reference voltage.