Direct Dielectric Bonding for Low-Stress 3D Die Stacking
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Solution Overview
Problem
Conventional methods for stacking integrated device dies in 3D integration face challenges such as die damage from assembly stresses, difficulty in stacking dies with different thicknesses and high pin counts, and the use of thick low coefficient of thermal expansion materials, which are costly and difficult to manufacture.
Innovation Solution
The direct gang bonding method involves simultaneously bonding elements without intervening adhesives, using a carrier with a polished dielectric surface, and depositing a dielectric layer over the elements to reduce thermal stresses and simplify the deposition process, allowing for covalent bonding at room temperature without external pressure or voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional die stacking methods are used, then dies can be assembled into 3D integration, but assembly stresses damage dies and reduce product yield
Solution Approach 1:
The patent applies preliminary action by preparing the bonding surfaces of dies in advance through mechanical polishing and chemical-mechanical polishing (CMP) to achieve atomic-level smoothness before bonding. This pre-preparation eliminates the need for high assembly stresses during the bonding process, thereby preventing die damage and improving product yield
Solution Approach 2:
The patent changes the surface roughness parameter of die bonding surfaces from conventional levels to atomic-level smoothness (less than 1 nanometer RMS). This parameter change enables direct bonding at lower stresses, resolving the contradiction between assembly stress and product yield
2Strength
If adhesive materials are used between dies, then bonding can be achieved, but thermal stresses increase and manufacturing complexity increases
Solution Approach 1:
The patent extracts and eliminates the adhesive layer from the die bonding process. By achieving direct bonding through ultra-smooth surface preparation, the adhesive material is completely removed, eliminating the source of thermal stress mismatch and simplifying the manufacturing process while maintaining bonding strength
Solution Approach 2:
The patent uses an intermediary approach by introducing a controlled plasma treatment or chemical activation step between surface preparation and bonding. This intermediary step enhances surface reactivity to enable direct bonding without adhesives, resolving both the bonding strength and manufacturing complexity issues
3Stress or pressure
If thick low coefficient of thermal expansion materials are used, then thermal stress can be reduced, but manufacturing cost and difficulty increase
Solution Approach 1:
The patent extracts and eliminates the thick low CTE material layer from the bonding structure. By achieving direct bonding between ultra-smooth die surfaces, the need for additional thermal stress management materials is removed, simultaneously reducing thermal stress issues and manufacturing complexity
Solution Approach 2:
The patent changes the bonding interface properties by achieving atomic-level surface smoothness, which fundamentally alters the thermal stress distribution. This parameter change eliminates the need for thick low CTE materials while maintaining stress reduction, improving ease of manufacture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the bonding strength of integrated device dies, reduces thermal stresses, and simplifies the manufacturing process, leading to improved product yield and reduced fabrication costs by eliminating the need for thick thermal expansion materials.
Implementation Method 1
allowing for covalent bonding at room temperature without external pressure or voltage
Implementation Method 2
depositing a dielectric layer over the elements to reduce thermal stresses
Data Source
AI summary
A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.