Direct DRAM to Flash Data Transfer via Module Controller
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Solution Overview
Problem
Current computer systems face inefficiencies in data transfer between main memory (DRAM) and secondary storage due to the need for multiple steps through temporary buffers, which increases CPU time and memory channel usage, leading to performance degradation.
Innovation Solution
The implementation of a Hypervault™ memory module with both volatile (DRAM) and non-volatile (Flash) subsystems, utilizing a module controller and data routing circuit to facilitate direct data transfers between DRAM and Flash memory, bypassing the need for temporary buffers by using a buffer memory to manage data at DRAM speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer between DRAM and secondary storage uses temporary buffers through multiple steps, then data can be transferred between different storage types, but CPU time and memory channel usage increase leading to performance degradation
Solution Approach 1:
The patent extracts the data transfer function from the CPU and memory channel by implementing a direct data path between DRAM and secondary storage through the module controller. This removes the need for temporary buffers and intermediate processing steps, allowing data to move directly between storage components without consuming CPU time or memory channel bandwidth.
Solution Approach 2:
The module controller acts as an intermediary device that enables direct data transfer between DRAM and secondary storage. It provides the necessary control logic and data paths to facilitate communication between the two storage types without requiring CPU intervention or using temporary buffers, thus resolving the contradiction between transfer capability and resource consumption.
2Ease of operation
If multiple memory channel operations are used for data transfers, then data can be moved between DRAM and secondary storage, but system performance degrades
Solution Approach 1:
The patent extracts the data transfer operations from the memory channel by creating a dedicated data path through the module controller. This allows data to be transferred between DRAM and secondary storage without occupying the memory channel, eliminating performance degradation while maintaining full transfer capability.
Solution Approach 2:
The patent segments the memory module functionality by separating the data transfer path from the main memory channel. The module controller creates an independent data movement subsystem that operates parallel to the memory channel, allowing simultaneous memory operations and storage transfers without interference.
Data Source
AI summary
A computer system comprises a processor, a memory module and input/output devices. The memory module includes a circuit board, a volatile memory unit mounted on the circuit board, a non-volatile memory unit mounted on the circuit board and a control circuit mounted on the circuit board. The volatile memory unit comprises DRAM devices, and the non-volatile memory unit comprises flash memory. The processor is configured to execute an operating system (OS) and an application program and to present a memory address space to the application program. The memory address space including a memory mapped input/output (MMIO) space mapped to the I/O devices, a pseudo MMIO (PMMIO) space mapped to the non-volatile memory unit, and a DRAM space mapped to the volatile memory unit, the PMMIO space including a system main memory local storage (MMLS) area and a memory channel storage area, wherein the DRAM space is partitioned into memory pages, and the MCS space is partitioned into storage blocks.