Direct Fractional Clock Divider for Low-Jitter Frequency Synthesis
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Solution Overview
Problem
Existing clock tree solutions for communications and processing devices face challenges in generating multiple output frequencies with non-integer relationships to the input clock frequency, requiring complex circuitry and high power consumption, while also struggling with phase noise and spur folding.
Innovation Solution
The implementation of direct fractional frequency dividers using dynamic divider circuits, delta-sigma modulators, and phase accumulators to generate output clock signals with adjustable phase and low jitter, eliminating the need for integer dividers and reducing power consumption by operating at lower frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a PLL-based clock tree is used to generate multiple output frequencies, then frequency versatility is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent divides the clock tree into multiple independent fractional frequency divider channels, each capable of generating different output frequencies autonomously. This segmentation allows each channel to be optimized independently while maintaining overall system versatility, reducing the complexity of managing a single centralized PLL for all frequency generation needs.
Solution Approach 2:
The fractional frequency divider circuit is designed as a universal building block that can generate multiple output frequencies through programmable division ratios. By making the divider multi-functional and configurable, the system achieves frequency versatility without requiring separate dedicated circuits for each frequency, thereby reducing overall device complexity.
2Device complexity
If integer frequency dividers are used to generate output frequencies, then device complexity is reduced, but frequency resolution and precision are limited
Solution Approach 1:
The patent implements dynamic frequency division where the division ratio can be programmably adjusted to achieve non-integer frequency relationships. This dynamic capability allows the circuit to achieve fine frequency resolution and precision while maintaining relatively simple circuit architecture, as the same hardware can be reconfigured for different division ratios rather than requiring multiple fixed-function dividers.
Solution Approach 2:
The fractional frequency divider allows changing the division ratio parameter to achieve different output frequencies with high precision. By programmably adjusting the division ratio parameter, the system achieves fine frequency resolution without increasing physical circuit complexity, as the same circuit structure can accommodate multiple precision frequency settings through parameter reconfiguration.
3Measurement precision
If high frequency intermediate clocks are used in PLL-based frequency synthesis, then output frequency precision is improved, but phase noise and time domain jitter increase
Solution Approach 1:
The patent employs periodic feedback through phase detectors that compare the divided output frequency with a reference, generating correction signals at regular intervals. This periodic action allows the system to maintain high output frequency precision while avoiding the continuous high-frequency operations that generate phase noise and jitter, as the feedback control operates periodically rather than continuously at high frequencies.
Solution Approach 2:
The fractional frequency divider incorporates feedback mechanisms where the divided output is compared against reference frequencies and correction signals are applied to maintain precision. This feedback approach enables high output frequency precision while operating at lower intermediate frequencies, thereby reducing the generation of phase noise and time domain jitter associated with high-frequency intermediate clocks.
4Measurement precision
If fractional frequency division is implemented using traditional architectures, then frequency resolution is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic frequency division where the division ratio can be programmably adjusted to achieve fine frequency resolution. This dynamic capability allows the circuit to achieve high frequency resolution while maintaining relatively low power consumption, as the same hardware can be reconfigured for different division ratios rather than requiring multiple parallel circuits operating simultaneously at high power.
Solution Approach 2:
The fractional frequency divider achieves high frequency resolution by programmably changing the division ratio parameter. This parameter-based approach to achieving fine frequency resolution avoids the need for complex parallel circuit architectures that would consume excessive power, as a single reconfigurable circuit can achieve the same resolution as multiple fixed circuits would require.
Data Source
AI summary
Disclosed examples include fractional frequency divider circuits, including a counter to provide phase shifted pulse output signals in response to counting of an adjustable integer number NK cycles of an input clock signal, an output circuit to provide an output clock signal having a first edge between first edges of the pulse output signals, as well as a delta-sigma modulator (DSM), clocked by the second pulse output signal to receive a first predetermined value and to provide a DSM output value, and a phase accumulator to receive a step input value representing a sum of the DSM output value and a second predetermined value. The phase accumulator provides a divisor input signal to the counter, and provides a phase adjustment value to the output circuit to control the position of the first edge of the output clock signal between the first edges of the pulse output signals.