Direct Injection Semiconductor Memory Device Reducing Power Consumption
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Solution Overview
Problem
Conventional semiconductor memory devices face issues with high power consumption and voltage swings during reading and writing operations, leading to inaccurate data state determination due to charge pumping and disturbance of unselected memory cells.
Innovation Solution
A direct injection semiconductor memory device is introduced, comprising a body region electrically floating and capacitively coupled to a word line, with a carrier injection line to inject charges, and specific voltage control methods to manage operations, reducing power consumption and minimizing disturbances to unselected cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional reading and writing operations are used with bias signals applied to source/drain regions and gates, then memory cells can be read and written, but power consumption increases and voltage swings cause disturbance to unselected memory cells
Solution Approach 1:
The patent segments the memory cell structure into distinct regions (first region coupled to source line, second region coupled to bit line, body region, third region coupled to carrier injection line) with independent control. This allows selective operation of individual cells without affecting unselected cells, reducing both power consumption and disturbance to neighboring cells while maintaining accurate data state determination.
2Ease of operation
If pulsing between positive and negative gate biases is used during read and write operations, then memory operations can be performed, but the net quantity of majority charge carriers in the electrically floating body region is reduced
Solution Approach 1:
The patent introduces a carrier injection line with a third region acting as an intermediary to compensate for charge carrier loss. This intermediary structure injects majority charge carriers into the electrically floating body region to offset carriers removed during pulsing operations, maintaining accurate data state determination while enabling continuous memory operations.
3Adaptability or versatility
If bias signals below threshold voltage potential are applied to the gate, then channel formation is controlled, but minority charge carriers become trapped in interface defects and combine with majority charge carriers
Solution Approach 1:
The patent converts the harmful effect of trapped minority charge carriers into a beneficial process by using them as part of a controlled charge pumping mechanism. The carrier injection line intentionally induces charge carrier trapping and release cycles that can be used to refresh and maintain the data state in the electrically floating body region, improving reliability rather than degrading it.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces power consumption and improves accuracy in data state determination by minimizing voltage swings and charge disturbances, enhancing the overall performance of semiconductor memory devices.
Implementation Method 1
a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating
Implementation Method 2
a third region coupled to a carrier injection line configured to inject charges into the body region through the second region
Data Source
AI summary
Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region coupled to a source line, a second region coupled to a bit line. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region coupled to a carrier injection line configured to inject charges into the body region through the second region.