Direct Injection Memory Voltage Biasing for Power and Accuracy
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Solution Overview
Problem
Conventional semiconductor memory devices face issues with high power consumption and inaccurate data state determination due to large voltage potential swings and charge pumping phenomena, which disturb unselected memory cells and reduce the net quantity of majority charge carriers in the electrically floating body region.
Innovation Solution
A direct injection semiconductor memory device method involving specific voltage potential applications to N-doped and P-type regions via bit lines, source lines, word lines, and carrier injection lines to perform read and write operations, including increasing or maintaining voltage potentials to reduce disturbances and accurately determine data states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional reading and writing operations are performed with large voltage potential swings, then read and write operations can be executed, but power consumption increases and unselected memory cells are disturbed
Solution Approach 1:
The patent applies parameter changes by using different voltage potential levels for different operational phases. Specifically, it maintains a first voltage potential during hold operations, transitions to a second voltage potential during read operations, and uses a third voltage potential during write operations. This dynamic adjustment of voltage parameters enables accurate data state determination while reducing power consumption compared to conventional approaches that use large voltage swings for all operations.
2Productivity
If large voltage potential swings are applied during read and write operations, then memory operations can be performed, but unselected memory cells are disturbed
Solution Approach 1:
The patent implements local quality by applying voltage potentials selectively to specific regions. It applies a first voltage potential to a first N-doped region via a bit line, a second voltage potential to a second N-doped region via a source line, and a third voltage potential to a P-type substrate via a carrier injection line. This localized application of different voltage potentials enables memory operations while minimizing disturbance to unselected memory cells through spatially differentiated voltage control.
3Reliability
If charge pumping occurs due to bias application below threshold voltage, then minority charge carriers are trapped in interface defects, but the net quantity of majority charge carriers in the electrically floating body region is reduced
Solution Approach 1:
The patent applies preliminary action by establishing a first voltage potential on the P-type substrate via the carrier injection line before performing read or write operations. This preliminary voltage application prevents charge pumping effects that would otherwise occur when bias is applied below threshold voltage, thereby maintaining the net quantity of majority charge carriers in the electrically floating body region and ensuring accurate data state determination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and improves the accuracy of data state determination by minimizing disturbances to unselected memory cells and maintaining the net quantity of majority charge carriers, enhancing the overall performance of semiconductor memory devices.
Implementation Method 1
a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating
Implementation Method 2
A decrease of majority charge carriers in the electrically floating body region may result from charge carriers being removed via drain region charge carrier removal, source region charge carrier removal, or drain and source region charge carrier removal, for example, using back gate pulsing
Data Source
AI summary
Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.